AD7821
INHERENT TRACK-AND-HOLD
A major benefit of the AD7821’s input structure is its ability to
measure a variety of high speed signals without the help of an
external track-and-hold. Any ADC which does not have a built-in
track-and-hold, regardless of its speed, requires the analog input to
remain stable to at least 1/2 LSB for the duration of the conver-
sion to maintain full accuracy. This requires the use of a
track-and-hold whenever the input is a high-speed signal. The
AD7821’s sampled-data comparators, by nature of their input
switching, inherently accomplish this track-and-hold function.
Although the conversion time for the AD7821 is 660 ns (WR-RD
mode, tWR + tRD + tACC1), the time for which VIN must be stable
to 1/2 LSB is much smaller. The AD7821 tracks VIN between
conversions only, and its value on the falling edge of WR or RD in
the WR-RD or RD modes, respectively, is the measured value.
Figure 6. AD7821 Equivalent Input Circuit
SINUSOIDAL INPUTS
The input capacitors must charge to the input voltage through the
on resistance of the analog switches (about 2 kΩ to 5 kΩ). In
addition, about 12 pF of input stray capacitance must be charged.
The bandwidth of the built-in track-and-hold is 100 kHz max
(150 kHz typ, 5 V p-p). This is limited by the analog bandwidth
of the comparators and timing skew between the comparator
switches. This means that the analog input frequency can be up
to 100 kHz without the aid of an external track-and-hold. The
Nyquist criterion requires that the sampling rate be at least
twice the input frequency (i.e., ≥2 ϫ 100 kHz). This requires an
ideal antialiasing filter with an infinite roll-off. To ease the prob-
lem of antialiasing filter design, the sampling rate is usually set
much greater than the Nyquist criterion. The maximum sampling
The analog input can be modeled as an equivalent RC network
as shown in Figure 7. As RS (source impedance) increases, the
input capacitance takes longer to charge.
The comparators track the analog input between conversions.
A minimum delay time (tP) of 350 ns is required between
conversions to allow for voltage source settling and comparator
tracking time. This allows input time constants of 50 ns without
settling time problems. Typical total input capacitance values of
55 pF allow RS to be 0.9 kΩ without lengthening tP to give VIN
more time to settle.
rate (fMAX) for the AD7821 in the WR-RD mode, (tRD < tINTL
can be calculated as follows:
)
1
fMAX
fMAX
=
=
tWR + tRD + tRI + tP
1
0.25 ×10−6 + 0.25 ×10−6 + 0.15 ×10−6 + 0.35 ×10−6
(
)
(
)
(
)
(
)
tWR = Write Pulsewidth
tRD = Delay Time between WR and RD Pulses
tRI = RD to INT Delay
tP = Delay Time between Conversions
Figure 7. RC Network Model
This permits a maximum sampling rate for the AD7821 of
1 MHz, which is much greater than the Nyquist criterion for
sampling a 100 kHz analog input signal.
INPUT TRANSIENTS
Transients on the analog input signal caused by charging current
flowing into VIN will not normally degrade the ADC’s perfor-
mance. In effect, the AD7821 does not “look” at the input when
these transients occur. The comparators’ inputs track VIN and are
not sampled until the falling edge of WR (WR-RD Mode) or
RD (RD Mode), so at least 350 ns (tP) is provided to charge the
ADC’s input capacitance. It is, therefore, not necessary to filter
out these transients with an external capacitor at the VIN terminal.
DIGITAL SIGNAL PROCESSING APPLICATIONS
In Digital Signal Processing (DSP) application areas such as voice
recognition, echo cancellation, and adaptive filtering, the dynamic
characteristics (Signal-to-Noise Ratio, Harmonic Distortion,
Intermodulation Distortion) of an ADC are critical. Since the
AD7821 is a very fast ADC with a built-in track-and-hold function,
it is specified dynamically as well as with standard dc specifications
(Total Unadjusted Error, and so on).
–8–
REV. B
ADI [ ADI ]
