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5962-89481022A 参数 Datasheet PDF下载

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型号: 5962-89481022A
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS 12位单片乘法DAC [CMOS 12-Bit Monolithic Multiplying DAC]
分类和应用: 转换器数模转换器
文件页数/大小: 8 页 / 230 K
品牌: ADI [ ADI ]
 浏览型号5962-89481022A的Datasheet PDF文件第1页浏览型号5962-89481022A的Datasheet PDF文件第2页浏览型号5962-89481022A的Datasheet PDF文件第4页浏览型号5962-89481022A的Datasheet PDF文件第5页浏览型号5962-89481022A的Datasheet PDF文件第6页浏览型号5962-89481022A的Datasheet PDF文件第7页浏览型号5962-89481022A的Datasheet PDF文件第8页  
AD7541A  
ABSOLUTE MAXIMUM RATINGS*  
Operating Temperature Range  
(TA = +25°C unless otherwise noted)  
Commercial (J, K Versions) . . . . . . . . . . . . . 0°C to +70°C  
Industrial (A, B Versions) . . . . . . . . . . . . . –25°C to +85°C  
Extended (S, T Versions) . . . . . . . . . . . . . –55°C to +125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V  
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 V  
Digital Input Voltage to GND . . . . . . . . –0.3 V, VDD + 0.3 V  
OUT 1, OUT 2 to GND . . . . . . . . . . . . –0.3 V, VDD + 0.3 V  
Power Dissipation (Any Package)  
*Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW  
Derates above +75°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
OUTPUT LEAKAGE CURRENT  
Current which appears at OUTI with the DAC loaded to all 0s  
or at OUT2 with the DAC loaded to all 1s.  
TERMINOLOGY  
RELATIVE ACCURACY  
Relative accuracy or endpoint nonlinearity is a measure of the  
maximum deviation from a straight line passing through the  
endpoints of the DAC transfer function. It is measured after  
adjusting for zero and full scale and is expressed in % of full-  
scale range or (sub)multiples of 1 LSB.  
MULTIPLYING FEEDTHROUGH ERROR  
AC error due to capacitive feedthrough from VREF terminal to  
OUT1 with DAC loaded to all 0s.  
OUTPUT CURRENT SETTLING TIME  
Time required for the output function of the DAC to settle to  
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full  
scale.  
DIFFERENTIAL NONLINEARITY  
Differential nonlinearity is the difference between the measured  
change and the ideal l LSB change between any two adjacent  
codes. A specified differential nonlinearity of ±1 LSB max over  
the operating temperature range insures monotonicity.  
PROPAGATION DELAY  
This is a measure of the internal delay of the circuit and is mea-  
sured from the time a digital input changes to the point at which  
the analog output at OUT1 reaches 90% of its final value.  
GAIN ERROR  
Gain error is a measure of the output error between an ideal  
DAC and the actual device output. For the AD7541A, ideal  
maximum output is  
DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)  
This is a measure of the amount of charge injected from the  
digital inputs to the analog outputs when the inputs change  
state. It is usually specified as the area of the glitch in nV secs  
and is measured with VREF = GND and a Model 50K as the  
output op amp, C1 (phase compensation) = 0 pF.  
4095  
4096  
(VREF ).  
Gain error is adjustable to zero using external trims as shown in  
Figures 4, 5 and 6.  
PIN CONFIGURATIONS  
DIP/SOIC  
LCCC  
PLCC  
1
2
3
4
5
6
7
8
9
18  
17  
16  
R
V
OUT1  
OUT2  
FEEDBACK  
3
2
1
20 19  
3
2
1
20 19  
IN  
REF  
V
(+)  
GND  
DD  
PIN 1  
IDENTIFIER  
GND  
BIT 1 (MSB)  
BIT 2  
4
5
6
18  
17  
16  
V
18  
17  
16  
15  
14  
4
5
6
V
DD  
GND  
BIT 1 (MSB)  
BIT 2  
DD  
15 BIT 12 (LSB)  
BIT 1 (MSB)  
BIT 2  
BIT 12 (LSB)  
BIT 11  
AD7541A  
BIT 12 (LSB)  
BIT 11  
AD7541A  
TOP VIEW  
AD7541A  
TOP VIEW  
(Not to Scale)  
TOP VIEW 14 BIT 11  
(Not to Scale)  
(Not to Scale)  
BIT 3 7  
BIT 4 8  
BIT 10  
BIT 3  
BIT 10  
BIT 9  
BIT 8  
13  
12  
11  
BIT 3  
15 BIT 10  
BIT 9  
7
8
BIT 9  
BIT 4  
BIT 4  
14  
BIT 5  
9
10 11 12 13  
9
10 11 12  
13  
BIT 6  
10 BIT 7  
NC = NO CONNECT  
NC = NO CONNECT  
REV. B  
–3–