AD664
Table II. AD664 Digital Truth Table
Function
DS1, DS0
LS
MS
TR
QS0, 1, 21
RD
CS
RST
Load 1st Rank (data)
DACA
DACB
DACC
DACD
00
01
10
11
0
0
0
0
1
1
1
1
1
1
1
1
Select Quad
Select Quad
Select Quad
Select Quad
1
1
1
1
1→0
1→0
1→0
1→0
1
1
1
1
Load 2nd Rank (data)
Readback 2nd Rank (data)
Reset
XX
1
1
1
XXX
1
1→0
1→0
X
1
1
0
Select D/A
XX
X
X
1
1
Select Quad
XXX
0
X
X
X
Transparent1
All DACs
DACA
XX
00
01
10
11
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
000
000
000
000
000
1
1
1
1
1
1→0
1→0
1→0
1→0
1→0
1
1
1
1
1
DACB
DACC
DACD
Mode Select1, 2
1st Rank
2nd Rank
XX
XX
0
1
0
0
1
1
00X
XXX
1
1
1→0
1→0
1
1
Readback Mode1
XX
X
0
1
00X
0
1→0
1
Update 2nd Rank
and Mode
XX
1
0
0
XXX
1
1→0
1
NOTES
X = Don’t Care.
1For 44-pin versions only. Allow the AD664 to be addressed in 4-bit nibble, 8-bit byte or 12-bit parallel words.
2For MS, TR, LS = 0, a MS 1st write occurs.
The following sections detail the timing requirements for
various data loading schemes. All of the timing specifica-
tions shown assume VIH = 2.4 V, VIL = 0.4 V, VCC = +15 V,
V
EE = –15 V and VLL = +5 V.
Load and Update One DAC Output
In this first example, the object is simply to change the output of
one of the four DACs on the AD664 chip. The procedure is to
select the address bits that indicate the DAC to be programmed,
pull LATCH SELECT (LS) low, pull CHIP SELECT (CS)
low, release LS and then release CS. When CS goes low, data
enters the first rank of the input latch. As soon as LS goes high,
the data is transferred into the second rank and produces the
new output voltage. During this transfer, MS, TR, RD and RST
should be held high.
Figure 9a. Update Output of a Single DAC
25؇C
MIN (ns)
TMIN to TMAX
MIN (ns)
SYMBOL
tLS
Preloading the First Rank of One DAC
*
0
0
In this case, the object is to load new data into the first rank of
one of the DACs but not the output. As in the previous case, the
address and data inputs are placed on the appropriate pins. LS
is then brought to “0” and then CS is asserted. Note that in this
situation, however, CS goes high before LS goes high. The in-
put data is prevented from getting to the second rank and affect-
ing the output voltage.
tDS
tDH
tLW
tCH
tAS
tAH
0
0
60
30
0
0
0
80
50
0
0
0
*FOR tLS > 0, THE WIDTH OF LS MUST BE
INCREASED BY THE SAME AMOUNT THAT
tLS IS GREATER THAN 0 ns.
Figure 9b. Update Output of a Single DAC Timing
D
REV.
–8–
ADI [ ADI ]
