AD7528
MICROPROCESSOR INTERFACE
ADDRESS BUS
A8–A15
A**
ADDRESS BUS
A0–A15
DAC A/DAC B
ADDRESS
DECODE
LOGIC
CPU
8085
CS
A**
DAC A
DAC A/DAC B
ADDRESS
DECODE
LOGIC
A + 1**
V
MA
WR
WR
DB0
DB7
AD7528*
CS
DAC A
CPU
6800
LATCH
8212
A + 1**
DAC B
ALE
AD7528*
WR
2
DB0
DB7
DAC B
ADDR/DATA BUS
AD0–AD7
*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
**A = DECODED 7528 ADDR DAC A
A + 1 = DECODED 7528 ADDR DAC B
D0–D7
DATA BUS
*ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY
**A = DECODED 7528 ADDR DAC A
A + 1 = DECODED 7528 ADDR DAC B
NOTE:
8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE
BOTH DACs WITH DATA FROM H AND L REGISTERS
Figure 11. AD7528 Dual DAC to 6800 CPU Interface
Figure 12. AD7528 Dual DAC to 8085 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
In the circuit of Figure 13 the AD7528 is used to implement a
programmable window comparator. DACs A and B are loaded
with the required upper and lower voltage limits for the test,
respectively. If the test input is not within the programmed
limits, the pass/fail output will indicate a fail (logic zero).
V
DD
TEST INPUT
V
0 TO –V
CC
REF
R
A
FB
1k⍀
OUT A
V
A
3
2
REF
7
DAC A
DB0
DB7
DATA
INPUTS
AD311
COMPARATOR
CS
AD7528
PASS/ FAIL
OUTPUT
WR
OUT B
2
3
DAC A/DAC B
7
DAC B
+V
REF
V
B
REF
AD311
COMPARATOR
R
B
FB
Figure 13. Digitally Programmable Window Comparator
(Upper and Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
In this state variable or universal filter configuration (Figure 14)
DACs A1 and B1 control the gain and Q of the filter character-
istic while DACs A2 and B2 control the cutoff frequency, fC.
DACs A2 and B2 must track accurately for the simple expres-
sion for fC to hold. This is readily accomplished by the AD7528.
Op amps are 2 × AD644. C3 compensates for the effects of op
amp gain bandwidth limitations.
The filter provides low pass, high pass and band pass outputs
and is ideally suited for applications where microprocessor
control of filter parameters is required, e.g., equalizer, tone
controls, etc.
Programmable range for component values shown is fC = 0 kHz
to 15 kHz and Q = 0.3 to 4.5.
R5
30k⍀
CIRCUIT EQUATIONS
C1= C2,R1= R2, R4 = R5
C1
1000pF
C2
1000pF
R4
30k⍀
C3
47pF
R3
10k⍀
1
HIGH
A1
fC =
LOW
A2
PASS
A3
A4
PASS
2 π R1C1
OUTPUT
OUTPUT
BAND
R3 RF
PASS
Q =
×
V
OUTPUT
V
DD
DD
R4 RFBB1
AD7528
DAC A1
RF
RS
AO = –
DAC B1
DAC A2
R1
DAC B2
R2
V
IN
AD7528
R
R
S
F
NOTE
DAC Equivalent Resistance
Equals
DB0–DB7
DATA 1
DB0–DB7
DATA 2
CS WR DAC A/DAC B
CS WR DAC A/DAC B
R
256 ×(DAC Ladder esistance)
DAC Digital Code
Figure 14. Digitally Controlled State Variable Filter
–7–
REV. B
ADI [ ADI ]
