(VREF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
AD7528–SPECIFICATIONS
VDD = +5 V
Version1 TA = +25°C TMIN, TMAX
VDD = +15 V
Parameter
TA= +25°C TMIN, TMAX
Units
Test Conditions/Comments
STATIC PERFORMANCE2
Resolution
Relative Accuracy
All
8
±1
±1/2
±1/2
±1
8
±1
±1/2
±1/2
±1
8
±1
±1/2
±1/2
±1
8
±1
±1/2
±1/2
±1
Bits
J, A, S
K, B, T
L, C, U
All
LSB max
LSB max
LSB max
LSB max
This is an Endpoint Linearity Specification
Differential Nonlinearity
Gain Error
All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Measured Using Internal RFB A and RFB B
Both DAC Latches Loaded with 11111111
Gain Error is Adjustable Using Circuits
of Figures 4 and 5
J, A, S
K, B, T
L, C, U
±4
±2
±1
±6
±4
±3
±4
±2
±1
±5
±3
±1
LSB max
LSB max
LSB max
Gain Temperature Coefficient3
∆Gain/∆Temperature
All
±0.007
±0.007
±0.0035
±0.0035
%/°C max
Output Leakage Current
OUT A (Pin 2)
OUT B (Pin 20)
All
All
All
±50
±50
8
±400
±400
8
±50
±50
8
±200
±200
8
nA max
nA max
kΩ min
kΩ max
DAC Latches Loaded with 00000000
Input Resistance (VREF A, VREF B)
Input Resistance TC = –300 ppm/°C, Typical
Input Resistance is 11 kΩ
15
15
15
15
VREF A/VREF B Input Resistance
Match
All
±1
±1
±1
±1
% max
DIGITAL INPUTS4
Input High Voltage
VIH
Input Low Voltage
VIL
All
All
All
2.4
0.8
±1
2.4
0.8
±10
13.5
1.5
±1
13.5
1.5
V min
V max
µA max
Input Current
IIN
±10
VIN = 0 or VDD
Input Capacitance
DB0–DB7
WR, CS, DAC A/DAC B
All
All
10
15
10
15
10
15
10
15
pF max
pF max
SWITCHING CHARACTERISTICS3
See Timing Diagram
Chip Select to Write Set Up Time
tCS
Chip Select to Write Hold Time
tCH
DAC Select to Write Set Up Time
tAS
DAC Select to Write Hold Time
tAH
Data Valid to Write Set Up Time
tDS
Data Valid to Write Hold Time
tDH
Write Pulsewidth
tWR
All
All
All
All
All
All
All
90
0
100
0
60
10
60
10
30
0
80
15
80
15
40
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
90
0
100
0
80
0
90
0
90
100
60
80
POWER SUPPLY
IDD
See Figure 3
All Digital Inputs VIL or VIH
All Digital Inputs 0 V or VDD
All
All
2
100
2
500
2
100
2
500
mA max
µA max
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
AC PERFORMANCE CHARACTERISTICS5
VDD = +5 V
VDD = +15 V
Parameter
Version1 TA = +25°C TMIN, TMAX TA= +25°C TMIN, TMAX Units
Test Conditions/Comments
% per % max ∆VDD = ±5%
DC SUPPLY REJECTION (∆GAIN/∆VDD
CURRENT SETTLING TIME2
)
All
All
0.02
350
0.04
400
0.01
180
0.02
200
ns max
To 1/2 LSB. OUT A/OUT B Load = 100 Ω.
WR = CS = 0 V. DB0–DB7 = 0 V to VDD or
VDD to 0 V
PROPAGATION DELAY (From Digital In-
put to 90% of Final Analog Output Current) All
VREF A = VREF B = +10 V
220
160
270
80
100
ns max
OUT A, OUT B Load = 100 Ω CEXT = 13 pF
WR = CS = 0 V DB0–DB7 = 0 V to VDD or
VDD to 0 V
DIGITAL-TO-ANALOG GLITCH IMPULSE All
OUTPUT CAPACITANCE
440
nV sec typ
For Code Transition 00000000 to 11111111
COUT
COUT
COUT
COUT
A
B
A
B
All
50
50
120
120
50
50
120
120
50
50
120
120
50
50
120
120
pF max
pF max
pF max
pF max
DAC Latches Loaded with 00000000
DAC Latches Loaded with 11111111
AC FEEDTHROUGH6
VREF A to OUT A
VREF B to OUT B
All
–70
–70
–65
–65
–70
–70
–65
–65
dB max
dB max
VREF A, VREF B = 20 V p-p Sine Wave
@ 100 kHz
–2–
REV. B
ADI [ ADI ]
