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5-330808-3 参数 Datasheet PDF下载

5-330808-3图片预览
型号: 5-330808-3
PDF下载: 下载PDF文件 查看货源
内容描述: 14位, 80 MSPS / 105 MSPS A / D转换器 [14-Bit, 80 MSPS/105 MSPS A/D Converter]
分类和应用: 转换器
文件页数/大小: 24 页 / 776 K
品牌: ADI [ ADI ]
 浏览型号5-330808-3的Datasheet PDF文件第1页浏览型号5-330808-3的Datasheet PDF文件第2页浏览型号5-330808-3的Datasheet PDF文件第3页浏览型号5-330808-3的Datasheet PDF文件第4页浏览型号5-330808-3的Datasheet PDF文件第6页浏览型号5-330808-3的Datasheet PDF文件第7页浏览型号5-330808-3的Datasheet PDF文件第8页浏览型号5-330808-3的Datasheet PDF文件第9页  
AD6645  
AD6645ASQ-80/  
AD6645ASV-80  
AD6645ASQ-105/  
AD6645ASV-105  
Test  
Parameter  
Temp  
Level  
Min  
Typ  
Max  
Min  
Typ  
Max  
Unit  
Conditions  
WORST HARMONIC (FOURTH OR HIGHER)  
Analog Input @ −1 dBFS  
2ꢀ°C  
Full  
2ꢀ°C  
Full  
2ꢀ°C  
2ꢀ°C  
2ꢀ°C  
2ꢀ°C  
2ꢀ°C  
V
II  
I
V
V
V
V
V
V
96.0  
8ꢀ.0 9ꢀ.0  
96.0  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
At 1ꢀ.ꢀ MHz  
At 30.ꢀ MHz  
At 37.7 MHz  
At 70.0 MHz  
At 1ꢀ0.0 MHz  
At 200.0 MHz  
At 30.ꢀ MHz1, 2  
At ꢀꢀ.0 MHz1, 3  
At 70.0 MHz1, 4  
86.0 9ꢀ.0  
90.0  
90.0  
90.0  
88.0  
100  
100  
90.0  
88.0  
TWO-TONE SFDR  
98.0  
98.0  
98.0  
dBFS  
dBFS  
dBFS  
TWO-TONE IMD REJECTION2, 3  
F1, F2 @ −7 dBFS  
2ꢀ°C  
2ꢀ°C  
V
V
90  
90  
dBc  
ANALOG INPUT BANDWIDTH  
270  
270  
MHz  
1 Analog input signal power swept from −10 dBFS to −100 dBFS.  
2 F1 = 30.ꢀ MHz, F2 = 31.ꢀ MHz.  
3 F1 = ꢀꢀ.2ꢀ MHz, F2 = ꢀ6.2ꢀ MHz.  
4 F1 = 69.1 MHz, F2 = 71.1 MHz.  
SWITCHING SPECIFICATIONS  
ENCODE  
AVCC = 5 V, DVCC = 3.3 V; ENCODE,  
, TMIN and TMAX at rated speed grade, unless otherwise noted.  
Table 4.  
AD6645ASQ-80/  
AD6645ASV-80  
AD6645ASQ-105/  
AD6645ASV-105  
Test  
Symbol Temp Level Min  
Parameter  
Typ  
Max  
Min  
Typ  
Max  
Unit  
ENCODE INPUT PARAMETERS1  
Maximum Conversion Rate  
Minimum Conversion Rate  
Full  
Full  
Full  
Full  
Full  
Full  
Full  
II  
80  
10ꢀ  
MSPS  
MSPS  
ns  
ns  
ns  
IV  
IV  
V
IV  
V
30  
30  
2
ENCODE Pulse Width High, tENCH  
ꢀ.62ꢀ  
ꢀ.62ꢀ  
4.286  
4.286  
6.2ꢀ  
4.7ꢀ  
2
ENCODE Pulse Width Low, tENCL  
6.2ꢀ  
12.ꢀ  
4.7ꢀ  
9.ꢀ  
ns  
ns  
ENCODE Period1  
tENC  
V
ENCODE/DATA-READY  
ENCODE Rising to Data-Ready Falling  
ENCODE Rising to Data-Ready Rising  
ꢀ0% Duty Cycle  
tDR  
tE_DR  
Full  
Full  
Full  
V
V
V
1.0  
7.3  
2.0  
tENCH + tDR  
8.3  
3.1  
9.4  
1.0  
ꢀ.7  
2.0  
tENCH + tDR  
6.7ꢀ  
3.1  
7.9  
ns  
ns  
ns  
ENCODE/DATA (D13:0), OVR  
ENCODE to DATA Falling Low  
ENCODE to DATA Rising Low3  
ENCODE to DATA Delay3 (Hold Time)  
ENCODE to DATA Delay (Setup Time)  
tE_FL  
tE_RL  
tH_E  
tS_E  
Full  
Full  
Full  
Full  
V
V
V
V
2.4  
1.4  
1.4  
4.7  
3.0  
3.0  
7.0  
4.7  
4.7  
2.4  
1.4  
1.4  
4.7  
3.0  
3.0  
7.0  
4.7  
4.7  
ns  
ns  
ns  
ns  
tENC  
tENC  
tE_FL(max)  
tE_FL(max)  
tENC  
tE_FL(typ)  
tENC  
tE_FL(typ)  
ns  
ns  
ns  
tENC  
tE_FL(min)  
10.0  
tENC −  
tE_FL(min)  
7.0  
ꢀ0% Duty Cycle  
Full  
V
ꢀ.3  
7.6  
2.3  
4.8  
Rev. D | Page ꢀ of 24