ACT8937A
Rev 1, 22-Oct-12
microprocessor must take control (by asserting
PWRHLD) before nPBIN is de-asserted. If the
microprocessor is unable to complete its power-up
routine successfully before the user releases the
push-button, the ACT8937A automatically shuts the
system down. This provides protection against
accidental or momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be implemented by simply adding an additional time
delay before asserting PWRHLD.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage
(typically OUT1) through a 10kꢀ or greater resistor.
Control Sequences
nRSTO Output
The ACT8937A features a variety of control
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
Samsung S5PC100, S5PC110 and S5PV210
processors.
nRSTO is an open-drain output which asserts low
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT5 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Enable/Disable Sequence
A typical enable sequence is initiated whenever the
following conditions occurs:
1) nPBIN is asserted low via 50Kꢀ resistance, or
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT1).
2) A valid input voltage is present at CHGIN, and
PWRHLD is asserted within 260msꢀ.
The enable sequence begins by enabling REG5.
When REG5 reaches its power-OK threshold,
nRSTO is asserted low, resetting the
microprocessor. REG2, REG3 and REG4 are
enabled after REG5 reaches its power-OK
threshold for 8ms2. When REG2 reaches its power-
OK threshold for 8ms2, REG1 and REG6 are
enabled. When REG2 reaches its power-OK
threshold for 16ms2, REG7 is enabled. If REG5 is
above its power-OK threshold when the reset timer
expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
Many of the ACT8937A's functions support
interrupt-generation as
a
result of various
conditions. These are typically masked by default,
but may be unmasked via the I2C interface. For
more information about the available fault
conditions, refer to the appropriate sections of this
datasheet.
During the boot sequence, the processor
automatically asserts PWREN(XPWRRGTON),
holding REG2, REG3, REG4, REG6 and REG7 ,
and the processor has to assert PWRHLD to keep
the ACT8937A enabled so that the system remains
powered after nPBIN is released.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as PWRHLD is asserted high. If
the processor does not assert PWRHLD before the
user releases the push-button, the boot-up
sequence is terminated and all regulators are
disabled. This provides protection against "false-
enable", when the push-button is accidentally
depressed, and also ensures that the system
remains enabled only if the processor successfully
Push-Button Control
The ACT8937A is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
ꢀ: Applicable only for ACT8937AQJ2##; When adapter at CHGIN in connected, PWRHLD has to be asserted within 260ms so that
the system remains powered, otherwise the PMU will be turned off automatically.
2: Typical value shown, actual delay time may vary from (T-1ms) x 88% to T x 112%, where T is the typical delay time setting.
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