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ACT8937AQJ106-T 参数 Datasheet PDF下载

ACT8937AQJ106-T图片预览
型号: ACT8937AQJ106-T
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的PMU三星S5PC100 , S5PC110和S5PV210处理器 [Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors]
分类和应用: PC
文件页数/大小: 45 页 / 845 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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ACT8937A  
Rev 1, 22-Oct-12  
completes the boot-up sequence.  
interrupts the processor. In response to this  
interrupt the processor should de-assert  
PWREN(XPWRRGTON), disabling REG2, REG3,  
REG4, REG6 and REG7. PWRHLD should remain  
asserted during SLEEP mode so that REG1 and  
REG5 remain enabled.  
As with the enable sequence, a typical disable  
sequence is initiated when the user presses the  
push-button, which interrupts the processor via the  
nPBSTAT output. The actual disable sequence is  
completely software-controlled, but typically  
involved initiating various “clean-up” processes  
before the processor finally de-asserts PWRHLD to  
disable the ACT8937A, and hence shuts the  
system down.  
Waking up from SLEEP mode is typically initiated  
when the user presses the push-button again,  
which enables REG2, REG3, REG4, REG6 and  
REG7 and asserts nPBSTAT, which interrupts the  
processor, the processors should respond by  
asserting PWREN(XPWRRGTON), which holds  
REG2, REG3, REG4, REG6 and REG7 so that  
normal operation may resume. An external interrupt  
, for instance a charger interrupt or a RTC interrupt,  
can also initiate a wake up sequence. When an  
external interrupt is sent to the processor, the  
processor should response by getting itself ready to  
wake up from SLEEP mode first, then assert  
PWREN(XPWRRGTON), which enables REG2,  
REG3, REG4, REG6 and REG7 so that the normal  
operation may resume.  
SLEEP/Wake-up Sequence  
The ACT8937A supports Samsung S5PC100,  
S5PC110 and S5PV210 processors’ SLEEP mode  
operation. Once a successful power-up routine has  
been completed, SLEEP mode may be initiated  
through  
a
variety of software-controlled  
mechanisms.  
SLEEP mode is typically initiated when the user  
presses the push-button during normal operation.  
Pressing the push-button asserts the nPBIN input,  
which asserts the nPBSTAT output, which  
Figure 3:  
Enable (from push-button) / Disable Sequence  
: Applicable only for ACT8937AQJ2##, when CHGIN input voltage is connected, PWRHLD has to be asserted within 260ms.  
Innovative PowerTM  
- 30 -  
www.active-semi.com  
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.  
I2CTM is a trademark of NXP.  
Copyright © 2012 Active-Semi, Inc.  
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