Active-Semi
PIN DESCRIPTIONS CONT’D
PIN
24
ACT8810
Rev 4, 01-Oct-09
NAME
nPBIN
DESCRIPTION
Master Enable Input. Drive nPBIN to GA through a 100kΩ resistor to enable the IC, drive nPBIN
directly to GA to assert a Hard-Reset condition. Refer to the
System Startup & Shutdown and
Control Sequence
sections for more information. nPBIN is internally pulled up to VSYS through a
50kΩ resistor.
Output Feedback Sense for REG3. Connect this pin directly to the output node to connect the
internal feedback network to the output voltage.
Power Ground for REG3. Connect GA, GP1, GP2, and GP3 together at a single point as close to
the IC as possible.
Switching Node Output for REG3. Connect this pin to the switching end of the inductor.
Power Input for REG3. Bypass to GP3 with a high quality ceramic capacitor placed as close as
possible to the IC.
RTC LDO Output Voltage. Capable of delivering up to 30mA of output current.
Output Voltage for REG5. Capable of delivering up to 360mA of output current. The output is
discharged to GA with 1kΩ when disabled.
Power Input for REG4, REG5, and REG6. Bypass to GA with a high quality ceramic capacitor
placed as close as possible to the IC.
Output Voltage for REG4. Capable of delivering up to 360mA of output current. The output is
discharged to GA with 1kΩ when disabled.
Active-Low Open-Drain Charger Status Output. nSTAT has a 5mA (typ) current limit, allowing it to
directly drive an indicator LED without additional external components. To generate a logic-level
output, connect nSTAT to an appropriate supply voltage (typically VSYS) through a 10kΩ or
greater pull-up resistor. See the
Charge Status Indication
section for more information.
Independent Enable Control Input for REG2. Drive ON2 to a logic high for normal operation, drive to
GA or a logic low to disable REG2. Do not leave ON2 floating.
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1, GP2, and GP3
together at a single point as close to the IC as possible.
Reference Noise Bypass. Connect a 0.01μF ceramic capacitor from REFBP to GA. This pin is
discharged to GA in shutdown.
Open-Drain Reset Output. nRSTO asserts low whenever REG1 is out of regulation, and remains low
for 260ms (typ) after REG1 reaches regulation.
Open-Drain Interrupt Output. nIRQ asserts any time nPBIN is asserted or an unmasked fault
condition exists. See the
nIRQ Output
section for more information.
Charging State Select Input.
25
26
27
28
29
30
31
32
OUT3
GP3
SW3
VP3
OUT6
OUT5
INL
OUT4
33
nSTAT
34
35, 37
36
38
39
ON2
GA
REFBP
nRSTO
nIRQ
40
When ACIN = 0 charge current is internally set; Drive CHGLEV to a logic-high for high-current USB
charging mode (maximum charge current is 500mA), drive CHGLEV to a logic-low for low-current
CHGLEV USB charging mode (maximum charge current is 100mA).
When ACIN = 1 charge current is externally set by R
ISET
; Drive CHGLEV to a logic-high to for high-
current charging mode (I
CHG
= K × 1000/R
ISET
(mA) where K = 640), drive CHGLEV to a logic-low for
low-current charging mode (I
CHG
= K × 500/R
ISET
(mA) where K = 640). Do not leave CHGLEV floating.
EP
EP
Exposed Pad. Must be soldered to ground on the PCB.
Innovative Power
TM
ActivePMU
TM
and
ActivePath
TM
are trademarks of Active-Semi.
I
2
C
TM
is a trademark of Philips Electronics.
-6-
www.active-semi.com
Copyright © 2009 Active-Semi, Inc.
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
