ACT8846
Rev 4, 25-May-16
Table 3:
ACT8846 and RK31x8 Signal Interface
ACT8846
PWREN
SCL
DIRECTION
ROCKCHIP RK31X8
GPIO6_B1
I2C1_SCL
I2C1_SDA
GPIO0_D7
GPIO0_D6
NPOR
SDA
VSELR2
GPIO1/VSELR3
nRSTO
nIRQ
GPIO6_A4
GPIO6_A2
GPIO6_B0
nPBSTAT
PWRHLD
Note: Typical connections shown, actual connections may vary.
0 after read. After Short Press, set WDSREN[ ] to 1
about 1s after nRSTO de-assert then clear
WDSREN[ ] for properly shutdown sequence.
Control Signals
Enable Inputs
The ACT8846 features a variety of control inputs,
which are used to enable and disable outputs
depending upon the desired mode of operation.
PWRHLD is a logic inputs, while nPBIN is a unique,
multi-function input.
Long Press / Power-cycle:
If the Manual Reset button is asserted for more
than 4s/10s, ACT8846 commences a power
cycle routine in which case all regulators are turned
off and then turned back on. A status bit, PCSTAT[
], is set after the power cycle. The PCSTAT[ ] bit is
automatically cleared to 0 after read.
nPBIN Multi-Function Input
The ACT8846 features the nPBIN multi-function
pin, which combines system enable/disable control
with a hardware reset function. Select either of the
two pin functions by asserting this pin, either
through a direct connection to GA as Manual Reset
input, or through a 50kꢀ resistor to GA for 32ms to
enable the IC, or through a 50kꢀ resistor to GA for
10s to disable the IC, as shown in Figure 2.
nPBSTAT Output
nPBSTAT is an open-drain output that reflects the
state of the nPBIN input; nPBSTAT is asserted low
whenever nPBIN is asserted, and is high-Z
otherwise. This output is typically used as an
interrupt signal to the processor, to initiate a
software-programmable routine such as operating
mode selection or to open a menu. Connect
nPBSTAT to an appropriate supply voltage through
a 10kꢀ or greater resistor.
Manual Reset Function
The second major function of the nPBIN input is to
provide a manual-reset input for the processor. To
manually-reset the processor, drive nPBIN directly
to GA through a low impedance (less than 2.5kꢀ).
An internal timer detects the duration of the MR
event:
Figure 2:
nPBIN Input
Short Press / Soft-Reset:
If the Manual Reset button is asserted for less than
4s/10s, ACT8846 commences
a
soft-reset
operation where nRSTO immediately asserts low,
then remains asserted low until the nPBIN input is
de-asserted and the reset time-out period expires.
A status bit, SRSTAT[ ] , is set after a soft-reset
event. The SRSTAT[ ] bit is automatically cleared to
: Only for ACT8846QM468 and ACT8846QM490-T.
: Soft-Reset function is disabled in ACT8846QM460 , ACT8846QM468 and ACT8846QM490.
: Only for ACT8846QM460.
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