ACT5830
Rev PrB, 05-Mar-08
SYSTEM MANAGEMENT
FUNCTIONAL DESCRIPTIONS
The ACT5830 offers a wide array of system man-
agement functions that allow it to be configured for
optimal performance in a wide range of applica-
tions.
Once the power-up routine is completed, the re-
maining LDOs can be enabled/disabled via either
the I2C interface or the TCXO_EN (LDO4), RX_EN
(LDO5), TX_EN (LDO6), and PWR_HOLD (REG
and LDO1) pins.
I²C Serial Interface
This start-up procedure requires that the push-
button be held until the microprocessor assumes
control of PWR_HOLD, providing protection against
inadvertent momentary assertions of the push-
button. If desired, longer “push-and-hold” times can
be easily implemented by simply adding an addi-
tional delay before assuming control of
PWR_HOLD. If the microprocessor is unable to
complete its power-up routine successfully before
the user lets go of the push-button, the ACT5830
will automatically shut itself down.
At the core of the ACT5830’s flexible architecture is
an I2C interface that permits optional programming
capability to enhance overall system performance.
Use standard I2C write-byte commands to program
the ACT5830 and read-byte commands to read the
IC’s status. Figure 1: I2C Serial Bus Timing provides
a standard timing diagram for the I2C protocol. The
ACT5830 always operates as a slave device, with
address 1010101.
System Startup & Shutdown
Once a successful power-up routine is completed,
the user can initiate a shutdown process by press-
ing the push-button a second time. Upon detecting
a second assertion of PWR_ON (by depressing the
push-button), the ACT5830 asserts nON to interrupt
the microprocessor which initiates an interrupt ser-
vice routine that will reveal that the user pressed
the push-button. If HF_PWR and CHG_OK are both
low, the microprocessor then initiates a power-down
routine, the final step of which will be to de-assert
PWR_HOLD, disabling REG and LDO1.
The ACT5830 features a flexible enable architec-
ture that allows it to support a variety of push-button
enable/disable schemes. Although other startup
routines are possible, a typical startup and shut-
down process would proceed as follows (referring
to Figure 2):
System startup is initiated whenever one of the fol-
lowing conditions occurs:
1) The user presses the push-button, asserting
PWR_ON high,
2) A valid supply (>4V) is connected to the
charger input (CHG_IN), or 3) a headset is con-
nected, asserting HF_PWR high.
The ACT5830 begins its system startup procedure
by enabling REG, LDO2 and LDO3, then LDO1 are
enabled when VBUCK or VOUT2 reaches 87% of
its final value. nRST is asserted low when VOUT1
reaches 87% of its final value, holding the micro-
processor in reset for a user-selectable reset period
of 65msec. If (VBUCK or VOUT2) and VOUT1 are
within 13% of their regulation voltages when the
reset timer expires, the ACT5830 de-asserts nRST
so that the microprocessor can begin its power up
sequence. Once the power-up routine is success-
fully completed, the microprocessor asserts
PWR_HOLD high to keep the ACT5830 enabled
after the push-button is released by the user.
Innovative PowerTM
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