ACT5880
Rev 2, 03-Sep-13
normal output state, the key press event only asserts
nPBSTAT (and the nIRQ when it is programmed so).
When OUT1 is disabled, the key press event starts
OUT1 and pulls the nRSTO low until the reset time-
out expires after the OUT1 is regulated, also asserts
nPBSTAT (and nIRQ when it is programmed so),
while no change to other rails.
state (refer to UVLOs and Low System Voltage
Alert section for more information).
In both modes, the nRSTO asserts against the
resuming of REG1.
Interrupts
The ACT5880 asserts interrupt as designated for a
function or when the house keeping circuit finds a
condition does not meet the reliable operation
situation, by pulling the nIRQ output low. The nIRQ is
an open-drain output, which is good for wired-or with
other interrupt request sources in the equipment
system. Every possible interrupt in the ACT5880 can
be masked by resetting/setting the respective
register bit. When interrupt asserted, the interrupt is
cleared by reading the respective register byte or
clearing a respective bit.
When the manual reset asserts, the ACT5880 pulls
the nRSTO output low instantly and holds it low until
reset time-out expires after the "Reset Key" is
released. As the nRSTO is kept low for a while after
the "Reset Key" is released and the power outputs of
the ACT5880 remain unchanged, it is assured that
the host processor is stopped if no any other of the 5
events holds it on, or is kept on if there is other event
holds it.
SLEEP Modes
There are totally 35 different sources/conditions for
interrupt assertion, refer to INTERRUPT
DESCRIBPTIONS section for a summary. It is
practically necessary to mask all the unused
interrupts to assure that the equipment system runs
efficiently, and to unmask the interrupts in case by
case basis for specified applications.
The ACT5880 features two sleep modes for low
quiescent current operation.
The sleep mode is a mode that the PWRHLD is
kept high by a circuit external to the ACT5880.
Comparing to the normal operation state with
different power rail configurations, the sleep mode
is a state the host processor keeps essential
system functions working. The power rail
configurations in sleep mode are in two subsets;
One subset keeps at least one of REG1 and REG2
in buck operation, while all the rest rails are flexible
to be programmed into any states, the other subset
could have both REG1 and REG2 buck mode off
while all LDO rails are only programmable in the
quiescent current mode, or are forced off if in the
low noise mode. As the power rails need to be
controlled through the host processor in this mode,
it needs to be carefully handled to keep the
essential system working.
House Keeping Functions
The house keeping functions for the ACT5880 itself
include the internal biasing, voltage reference
sharing in different blocks, UVLO (Under Voltage
Lock-Out), regulation status monitoring, over
current protection and over temperature protection.
The house-keeping functions assure the ACT5880
only operates reliably in proper system situation,
asserts interrupt to the system or shutdown the
ACT5880 when necessary condition does not meet.
Refer to the following sections for details.
The VSYS and the REFBP
The deep sleep mode further reduces the quiescent
current by stopping all other circuits in the ACT5880
by releasing the PWRHLD to low. In this mode only
the always-on regulator, and the linear regulation
circuit of the REG2 stay working.
The VSYS is the internal bias rail bypass node, the
REFBP is the bypass node for the on-chip
reference. The VSYS is driven by an internal pre-
regulation circuit, whose output is automatically
routed to connect the VBAT when there is no input
power at CHGIN is available.
In deep sleep mode, the operation resumes normal
by asserting PWRHLD (or any of nPBIN, HFPWR,
ACOK or RTC alarm wake-up events), when REG2
starts its buck regulation and other regulators
resume their previous states before the removing of
PWRHLD. This implies that the deep sleep state
has to be put from an operation state of the system
by de-asserting PWRHLD. Other ways like turning
off the I/O power which may turns the PWRHLD off
consequently, may put the system in a state that it
could not resume by the assertion of PWRHLD (or
any of the nPBIN HFPWR, ACOK or RTC alarm
wake-up), until the reloading of power on default
Proper bypass on those nodes reduces the noise
and improves the PSRR of every regulator.
Capacitors around 47nF~68nF for the REFBP and
1μF~2.2μF for the VSYS are recommended for their
bypassing.
UVLOs and Low System Voltage Alert
The ACT5880 has a system UVLO, a VVSYS
comparator for low system voltage alert and UVLOs
for step-down and step-up DC/DCs. The system
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