ACT5880
Rev 2, 03-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
DEFAULT
and
ACCESS
ADDRESS
and BIT
BLOCK
NAME
DESCRIPTION
Reserved for future use.
Reserved for future use.
7
6
RFU
RFU
x
x
WE/R
WE/R
Write and read for different functions, as flag bit or mask bit, for
the HFPWR assertion interrupt. Write 1 allow interrupt, write 0
mask interrupt; Read 1 when interrupt asserted, 0 if no interrupt.
Also see DATAB[ ], POSB[ ] and NEGB[ ] for the status and
conditions.
5
4
STB
STA
0
1
W/R
W/R
Write and read for different functions, as flag bit or mask bit, for
the "enable key" push-button assertion interrupt. Write 1 allow
interrupt, write 0 mask interrupt; Read 1 when interrupt asserted,
0 if no interrupt. Also see DATAA[ ], POSA[ ] for the status and
conditions.
0x6C
3
2
RFU
RFU
x
x
WE/R Reserved for future use.
Reserved for future use.
WE/R
W/R
This bit needs to be set 1 for asserting interrupt when HFPWR
asserted.
1
0
DATAB
DATAA
0
0
SYS
This bit needs to be set 1 for asserting interrupt when "enable
key" asserted.
W/R
Reserved for future use.
Reserved for future use.
7
6
RFU
RFU
x
x
WE/R
WE/R
This bit needs to be set 1 for asserting interrupt when HFPWR
asserted.
5
4
POSB
POSA
0
1
W/R
This bit needs to be set 1 for asserting interrupt when "enable
key" asserted.
W/R
0x6D
Reserved for future use.
3
2
RFU
RFU
x
x
WE/R
WE/R Reserved for future use.
This bit needs to be set 1 for asserting interrupt when HFPWR
de-asserted.
1
0
NEGB
RFU
0
x
W/R
Reserved for future use.
WE/R
Note:
W/R: Write and read accessible. R: Read accessible, writing to the bit does not make change to the volume. WE/R: Write
and read accessible, write exact what it is before to avoid unexpected behavior. X is uncertain volume.
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