ACT4910QW
Rev 1.0, 15-Sept-2017
then retries to softstart again. The following equation
calculates the minimum allowable softstart time.
Where FSW_max is the maximum allowable frequency,
VSTR is the storage voltage, and VOUT is the output
voltage during supplement mode.
ꢨ
ꢔꢞꢩꢗ∗ꢀꢟ
ꢠꢡꢢ
ꢔ
ꢗ
ꢣ
ꢦꢧ ꢘꢀ
ꢠꢡꢢꢀ
Equation 3
ꢓꢓ_ꢞꢤꢥ
ꢔ ꢗ
ꢬ
ꢪ.ꢫ∗ꢋ
ꢂꢃꢂꢄ
Output Voltage Setting
The buck converter output voltage is programmed by an
external resistor divider connected between the VOUT
pin and VSS, with the center tap connected to the FB
pin. The buck output voltage can be set above, below,
or equal to the input voltage supplement threshold.
When the input voltage drops below this threshold, the
IC enters supplement mode and regulates the output to
the programmed buck voltage. Although the buck
converter immediately starts up when the IC enters
supplement mode, the output voltage still has a small,
but finite drop in output voltage between the time the
eFuse turns off and the buck converter is fully on. This
voltage drop should be considered when setting the
output voltage. The following equation calculates the
correct resistor values to set the desired output voltage.
Where COUT is the sum of the output capacitance and
storage capacitance in mF, VOUT is the output voltage in
volts, and IILIM is the eFuse current limit in Amperes
programmed by the ILIM resistor.
Buck Converter
General Description
The ACT4910 contains current-mode, synchronous
PWM step-down converter that achieves peak
efficiencies of 95%. The buck converter minimizes noise
in sensitive applications and allows the use of small
external components. It is highly flexible with external
component selection and can be reconfigured via I2C
registers. External components set the output voltage
and compensation while I2C registers set the switching
frequency and current limit. The buck converter
operates in fixed frequency PWM mode. Its switching
frequency is programmable between 320kHz to 1130
kHz via the I2C register BK_FREQ[2:0] which allows the
system to be optimized for different applications. Its
current limit is adjustable between 5A to 9A, allowing for
further system optimization. The output voltage is
externally programmable between 1.8V and 18V.
ꢴ1 ꢘ R2 ∗ꢀꢵꢟꢟꢶꢷꢸ ꢻ 1ꢼ
Equation 4
ꢹꢺ
Where R1 is the top feedback resistor, R2 is the bottom
feedback resistor, VOUT is the desired output voltage,
and VFB is the fixed 1.2V reference voltage on the FB
pin. Choose R2 in the range of 10kohm. Smaller
resistor values are acceptable, but larger values will
affect voltage accuracy due to bias currents into the FB
pin.
Protection
The buck converter generates a regulated output
voltage at the VOUT pin from the storage capacitors
when the IC enters supplement mode. This provides the
backup power when the system experiences fault
conditions. After the IC exits the SOFTSTART state, the
buck converter is enabled but remains turned off. It
automatically turns on when the IC enters supplement
mode, and remains on until the storage capacitors
discharge to 3.6V.
The buck converter has several protection mechanisms
to insure safe operation. It stops operation when input
voltage from storage cap reaches STR_UVLO (3.6V) or
when the output voltage drops below the power good
threshold which is fixed at 93% of the output setpoint. It
also stops operating when the output voltage is above
the over voltage threshold which is fixed at 110% of the
output voltage setpoint. The output undervoltage
protection can be masked by the I2C register bit
Mask_BK_UV REG0x38 [0].
Frequency Setting
Higher switching frequencies result in smaller solution
sizes at the cost of slightly lower efficiency. Lower
switching frequencies result in larger solution sizes
with higher efficiency. The maximum allowable
switching frequency for any given design is limited by
the following equation.
The buck converter provides overcurrent and short
circuit protection. Overcurrent protection is achieved
with cycle-by-cycle current limiting. The peak current
threshold is set between 5Aand 9Aby the BK_CLIM bits.
If the peak current reaches the programmed threshold,
the IC turns off the power FET. This condition typically
results in shutdown due to an output voltage UV
condition due to the shortened switching cycle.
ꢟ
ꢠꢡꢢ
ꢖꢭꢮ_ꢞꢯꢰ ꢀꢱ ꢟ
Equation 3
∗ꢲꢳꢪꢥꢭ
ꢝꢢꢑ
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21
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