ACT410
Rev 3, 27-Feb-14
TYPICAL APPLICATION CONT’D
An EFD15 core is selected for the transformer.
Two 820µF electrolytic capacitors are used to keep
the ripple small.
From
the
manufacture’s
catalogue
recommendation, the gapped core with an effective
inductance ALE of 64 nH/T2 is selected. The turn of
the primary winding is:
PCB Layout Guideline
Good PCB layout is critical to have optimal
performance. Decoupling capacitor (C4) and
feedback resistor (R5/R6) should be placed close to
VDD and FB pin respectively. There are two main
power path loops. One is formed by C1/C2, primary
winding, Mosfet transistor and current sense
resistor (R9). The other is secondary winding,
rectifier D4 and output capacitors (C7/C6). Keep
these loop areas as small as possible. Connecting
high current ground returns, the input capacitor
ground lead, and the ACT410 GND pin to a single
point (star ground configuration).
LP
0.37mH
64nH / T2
(13)
NP =
=
= 76T
ALE
The turns of secondary and auxiliary winding can
be derived accordingly:
Ns
1
NS =
×Np =
×76 ≈ 7T
(14)
(15)
Np
11.32
NA
NS
NA =
×Ns = 2.28 ×7 ≈ 20T
Determining the value of the current sense resistor
(R9) uses the peak current in the design. Since the
ACT410 internal current limit is set to 1V, the
design of the current sense resistor is given by:
VCS
RCS
=
2×IOUT _OCP ×VOUT
LP ×FSW ×ηsystem
(16)
1
=
≈1.07.Ω
2×2.6×5
0.37mH×100kHz×0.75
Where Fsw is the frequency at 4.75V CC mode.
The voltage feedback resistors are selected
according to the Ioccmax and Vo. The design
Io_cc max is given by:
Np
Rfb1 × Rfb 2
VO + VD
fs =
×
×
(17)
Vcs
Ns Rfb1 + Rfb 2
Lp ×
× Kf _ sw
Rcs
The design Vo is given by:
Rfb1
Rfb2
Ns
Na
(18)
Vo = (1 +
)×
×VFB −VD
Where k is IC constant and K=0.000075, then we
can get the value:
(19)
Rfb1 = 68K,Rfb2 =11.5K
When selecting the output capacitor, a low ESR
electrolytic capacitor is recommended to minimize
ripple from the current ripple. The approximate
equation for the output capacitance value is given
by:
IOUT
2
COUT
=
=
= 364μF
(20)
fsw ×V
110k ×50mV
RIPPLE
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