ACT410
Rev 3, 27-Feb-14
TYPICAL APPLICATION CONT’D
Where ŋ is the estimated circuit efficiency, fL is the
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2х10µF electrolytic capacitors.
Design Example
The design example below gives the procedure for
a DCM fly back converter using an ACT410. Refer
to Application Circuit Figure 2, the design for an
adapter application starts with the following
specification:
The maximum duty cycle is set to be 35% at low
line voltage 85VAC and the circuit efficiency is
estimated to be 75%. Then the maximum average
input current is:
Input Voltage Range
Output Power, PO
90VAC - 265VAC, 50/60Hz
10W
5V
VOUT × IOUT
_ CC
IIN
=
_ MAX
Output Voltage, VOUTCV
Full Load Current, IOUTFL
CC Current, IOUTMAX
System Efficiency CV, η
(5)
V INDC
× η
_ MIN
2A
12 × 2 .3
100 × 0 .75
=
= 153 mA
2-2.6A
0.75
The maximum input primary peak current:
2 × LI
DMAX
2 ×153
0.35
N
ILIM
=
=
= 874 mA
(6)
The operation for the circuit shown in Figure 1 is as
follows: the rectifier bridge BD1 and the capacitor
C1/C2 convert the AC line voltage to DC. This
voltage supplies the primary winding of the
transformer T1 and the startup resistor R7/R8 to
VDD pin of ACT410 and C4. The primary power
current path is formed by the transformer’s primary
winding, the mosfet, and the current sense resistor
R9. The resistors R3, R2, diode D2 and capacitor
C3 create a snubber clamping network that protects
Q1 from voltage spike from the transformer primary
winding leakage inductance. The network
consisting of capacitor C4, diode D3 and resistor
R4 provides a VDD supply voltage for ACT410 from
the auxiliary winding of the transformer. The resistor
R4 is optional, which filters out spikes and noise to
makes VDD more stable. C4 is the decoupling
capacitor of the supply voltage and energy storage
component for startup. During power startup, the
current charges C4 through startup resistor R7/R8
from the rectified high voltage. The diode D4 and
the capacitor C7/L2/C6 rectify filter the output
voltage. The resistor divider consists of R5 and R6
programs the output voltage.
The primary inductance of the transformer:
VINDC _ MIN Dmax
Lp
=
ILIM × fs
(7)
(8)
100 × 0.35
874 mA ×110 k
=
= 0.37 mH
The maximum primary turns on time:
ILIM
TON
= Lp
_ MAX
VINDC
_ MIN
0.37 mH × 874 mA
=
= 3.23 μs
100
The ringing periods from primary inductance with
mosfet Drain-Source capacitor:
TRINGING_MAX = 2π Lp _MAXCDS _MAX
(9)
= 2×3.14× 0.37mH×(1+7%)×100PF =1.25μs
Design only an half ringing cycle at maximum load
in minimum low line, so secondly reset time:
TRST =TSW -TON_MAX -0.5TRINGING_MAX
(10)
=1/ 110kHz-3.23μs-0.5×1.25μs = 5.24μs
Since a bridge rectifier and bulk input capacitors are
used, the resulting minimum and maximum DC
input voltages can be calculated:
Base on conservation of energy and transformer
transform identity, the primary to secondary turns
ratio NP/NS:
1
VIN
NP
NS
TON
_ MIN
2POUT
(
- tC )
=
×
2fL
η × CIN
VINDC
=
2VIN2AC
_ MIN
TRST VOUT + VD
100
5.24 5 + 0.45
(11)
_ MIN
3.23
(3)
=
×
= 11 .31
1
2 ×10 .5 × (
- 3.5ms )
2 × 85 2
-
2 × 47
0.75 × 2 ×10 μF
=
≈100 V
The auxiliary to secondary turns ratio NA/NS:
N A
N S
VDD + VD '
VOUT + VD
12 + 0.45
5 + 0.45
=
=
= 2.28
VIN ( MAX
=
2 ×VIN ( MAX
)AC
(12)
)DC
(4)
=
2 ×(265 VAC ) = 375 V
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