ACT364
Rev 4, 14-Nov-12
TYPICAL APPLICATION CONT’D
where η is the estimated circuit efficiency, fL is the
line frequency, tC is the estimated rectifier
conduction time, CIN is empirically selected to be
2 × 6.8µF electrolytic capacitors based on the
3µF/W rule of thumb.
LP
1.5mH
(11)
NP
=
=
= 140
ALE
76 nH / T 2
The number of turns of secondary and auxiliary
windings can be derived when Np/Ns=20:
NS
NP
1
When the transistor is turned off, the voltage on the
transistor’s collector consists of the input voltage
and the reflected voltage from the transformer’s
secondary winding. There is a ringing on the rising
top edge of the flyback voltage due to the leakage
inductance of the transformer. This ringing is
clamped by a RCD network if it is used. Design this
clamped voltage as 50V below the breakdown of
the NPN transistor. The flyback voltage has to be
considered with selection of the maximum reverse
voltage rating of secondary rectifier diode. If a 40V
Schottky diode is used, then the flyback voltage can
be calculated:
NS
=
× NP
=
×140 = 7
(12)
20
NA
NS
NA
=
× NS = 2.7 ×7 = 19
(13)
The current sense resistance (RCS) determines the
current limit value based on the following equation:
0.9×V
0.9×0.396
CSLIM
R
=
=
=0.983R
CS
(
IOUTFL+IOUTMAX
)
×V
(
1+1.3
)
×5
0.69
OUT
(14)
η
⎛
⎞
⎛
⎞
⎟
system
1.5×75×
⎜
⎜
⎟
⎟
⎜
L ×fSW
×
P
0.89
ηxfm
⎝
⎠
⎝
⎠
The voltage feedback resistors are selected
according to below equation:
V
INDCMAX×(VOUTCV +VDS
)
375×(5 +0.4)
40×0.8 −5
VRO
=
=
=75V
(5)
VDREV −VOUTCV
NA LP
×
19 1.5
where VDS is the Schottky diode forward voltage,
VDREV is the maximum reverse voltage rating of the
diode and VOUTCV is the output voltage.
RFB1
=
×K =
×
×245122 ≈ 49.9k (15)
NP RCS
140
1
Where K is IC constant and K = 245122.
The maximum duty cycle is set to be 45% at low
line voltage 85VAC and the circuit efficiency is
estimated to be 70%. Then the full load input
current is:
VFB
RFB2
=
RFB1
NA
NS
(VOUTCV +VDS
)
−VFB
(16)
2.20
VOUTCV × IOUTPL
VINDCMIN ×η
5 ×1
90 ×70%
=
× 49.9 = 8.87k
IIN
=
=
= 79.36mA
(6)
(5 + 0.4 )× 2.7 − 2.20
When selecting the output capacitor, a low ESR
electrolytic capacitor is recommended to minimize
ripple from the current ripple. The approximate
equation for the output capacitance value is given by:
The maximum input primary peak current at full
load base on duty of 45%:
2 × IIN
2 × 79 .36
IPK
=
=
= 352 .7 mA
(7)
D
45 %
IOUTCC×D
fSW ×△VRIPPLE 75kHz×50mV
1×0.45
COUT
=
=
=120μF
The primary inductance of the transformer:
(17)
V
INDCMIN×D
90×45%
352.7mA×75kHz
(8)
LP =
=
≈1.5mH
A 470µF electrolytic capacitor is used to keep the
ripple small.
IPK ×fSW
ACT364 needs to work in DCM in all conditions,
thus NP/NS should meet
PCB Layout Guideline
LP ×IPK
LP ×IPK
0.9
fSW
NP
NS
+
<
⇒
>16
Good PCB layout is critical to have optimal
performance. Decoupling capacitor (C4), current
sense resistor (R9) and feedback resistor (R5/R6)
should be placed close to VDD, CS and FB pins
respectively. There are two main power path loops.
One is formed by C1/C2, primary winding, NPN
transistor and the ACT364. The other is the
secondary winding, rectifier D8 and output
capacitors (C5). Keep these loop areas as small as
possible. Connect high current ground returns, the
input capacitor ground lead, and the ACT364 G pin
NP
NS
(9)
V
INDCMIN
(VOUTCV +VDS )×
The auxiliary to secondary turns ratio NA/NS:
NA
NS
VDD +VDA +VR
OUTCV+VDS +V
14+0.38+1
5+0.40+0.3
=
=
= 2.7
(10)
V
CORD
Where VDA is diode forward voltage of the auxiliary
side and VR is the resister voltage.
An EFD15 transformer gapped core with an
effective inductance ALE of 76nH/T2 is selected.
The number of turns of the primary winding is:
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