v5.9
®
ProASICPLUS® Flash Family FPGAs
High Performance Routing Hierarchy
Features and Benefits
High Capacity
•
•
•
•
Ultra-Fast Local and Long-Line Network
High-Speed Very Long-Line Network
High-Performance, Low Skew, Splittable Global Network
100% Routability and Utilization
Commercial and Industrial
•
•
•
75,000 to 1 Million System Gates
27 K to 198 Kbits of Two-Port SRAM
66 to 712 User I/Os
I/O
•
•
Schmitt-Trigger Option on Every Input
2.5 V / 3.3 V Support with Individually-Selectable Voltage
and Slew Rate
Military
•
•
•
•
Bidirectional Global I/Os
•
•
•
300, 000 to 1 Million System Gates
72 K to 198 Kbits of Two Port SRAM
158 to 712 User I/Os
Compliance with PCI Specification Revision 2.2
Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant
PLUS
Pin-Compatible Packages across the ProASIC
Family
Reprogrammable Flash Technology
Unique Clock Conditioning Circuitry
•
•
•
•
•
•
0.22 µm 4 LM Flash-Based CMOS Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
No Configuration Device Required
Retains Programmed Design during Power-Down/Up Cycles
Mil/Aero Devices Operate over Full Military Temperature
Range
•
PLL with Flexible Phase, Multiply/Divide, and Delay
Capabilities
Internal and/or External Dynamic PLL Configuration
Two LVPECL Differential Pairs for Clock or Data Inputs
•
•
Standard FPGA and ASIC Design Flow
•
•
Flexibility with Choice of Industry-Standard Front-End Tools
Efficient Design through Front-End Timing and Gate
Optimization
Performance
•
3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military
temperature)
ISP Support
•
•
Two Integrated PLLs
•
In-System Programming (ISP) via JTAG Port
External System Performance up to 150 MHz
SRAMs and FIFOs
Secure Programming
•
SmartGen Netlist Generation Ensures Optimal Usage of
Embedded Memory Blocks
24 SRAM and FIFO Configurations with Synchronous and
Asynchronous Operation up to 150 MHz (typical)
®
•
The Industry’s Most Effective Security Key (FlashLock )
•
Low Power
•
•
•
Low Impedance Flash Switches
Segmented Hierarchical Routing Structure
Small, Efficient, Configurable (Combinatorial or Sequential)
Logic Cells
Table 1 • ProASICPLUS Product Profile
1
1
1
Device
Maximum System Gates
Tiles (Registers)
Embedded RAM Bits (k=1,024 bits)
APA075
75,000
3,072
27 k
12
APA150
150,000
6,144
36k
16
APA300
APA450
450,000
12,288
108 k
48
APA600
APA750
750,000
32,768
144 k
64
APA1000
300,000
8,192
72 k
32
600,000
21,504
126 k
56
1,000,000
56,320
198 k
88
Embedded RAM Blocks (256x9)
LVPECL
2
2
2
2
2
2
2
PLL
2
2
2
2
2
2
2
Global Networks
Maximum Clocks
Maximum User I/Os
JTAG ISP
4
24
158
Yes
Yes
4
32
242
Yes
Yes
4
32
290
Yes
Yes
4
48
344
Yes
Yes
4
56
454
Yes
Yes
4
64
562
Yes
Yes
4
88
712
Yes
Yes
PCI
Package (by pin count)
TQFP
PQFP
100, 144
208
100
208
456
–
208
456
–
208
456
–
208
456
–
208
456
–
208
456
PBGA
–
FBGA
CQFP
CCGA/LGA
144
144, 256
144, 256
208, 352
144, 256, 484 256, 484, 676
676, 896
896, 1152
208, 352
624
2
208, 352
624
2
Notes:
1. Available as Commercial/Industrial and Military/MIL-STD-883B devices.
2. These packages are available only for Military/MIL-STD-883B devices.
December 2009
i
© 2009 Actel Corporation
See the Actel website for the latest version of the datasheet.
ACTEL [ Actel Corporation ]
