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APA300-TQG1152PP 参数 Datasheet PDF下载

APA300-TQG1152PP图片预览
型号: APA300-TQG1152PP
PDF下载: 下载PDF文件 查看货源
内容描述: 的ProASIC闪存系列FPGA [ProASIC Flash Family FPGAs]
分类和应用: 闪存
文件页数/大小: 178 页 / 5078 K
品牌: ACTEL [ Actel Corporation ]
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PLUS  
ProASIC  
Flash Family FPGAs  
PLUS  
the appropriate logic cell inputs and outputs. Dedicated  
high-performance lines are connected as needed for fast,  
low-skew global signal distribution throughout the core.  
Maximum core utilization is possible for virtually any  
design.  
ProASICPLUS devices also contain embedded, two-port  
SRAM blocks with built-in FIFO/RAM control logic.  
ProASIC  
Architecture  
The proprietary ProASICPLUS architecture provides  
granularity comparable to gate arrays.  
The ProASICPLUS device core consists of a Sea-of-Tiles  
(Figure 1-1). Each tile can be configured as a three-input  
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by  
programming  
the  
appropriate  
flash  
switch  
Programming  
options  
include  
synchronous  
or  
interconnections (Figure 1-2 and Figure 1-3 on page 1-3).  
Tiles and larger functions are connected with any of the  
four levels of routing hierarchy. Flash switches are  
distributed throughout the device to provide  
nonvolatile, reconfigurable interconnect programming.  
Flash switches are programmed to connect signal lines to  
asynchronous operation, two-port RAM configurations,  
user-defined depth and width, and parity generation or  
checking.  
Refer  
to  
the  
"Embedded  
Memory  
Specifications" section on page 2-54 for more  
information.  
RAM Block  
256x9 Two-Port SRAM  
or FIFO Block  
I/Os  
Logic Tile  
RAM Block  
256x9 Two Port SRAM  
or FIFO Block  
Figure 1-1 The ProASICPLUS Device Architecture  
Switch In  
Floating Gate  
Sensing  
Switching  
Word  
Switch Out  
Figure 1-2 Flash Switch  
1-2  
v5.9