Device Architecture
Sequential Timing Characteristics
Table 2-2 • Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Description
Clock-to-Q of the Core Register
Parameter
tCLKQ
–2
–1
Std.
0.74
0.57
0.00
0.61
0.00
0.53
0.53
0.00
0.30
0.00
0.30
0.30
0.30
0.43
0.48
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.55
0.43
0.00
0.45
0.00
0.40
0.40
0.00
0.22
0.00
0.22
0.63
0.49
0.00
0.52
0.00
0.45
0.45
0.00
0.25
0.00
0.25
0.25
0.25
0.37
0.41
tSUD
Data Setup Time for the Core Register
tHD
Data Hold Time for the Core Register
tSUE
Enable Setup Time for the Core Register
tHE
Enable Hold Time for the Core Register
tCLR2Q
tPRE2Q
tREMCLR
tRECCLR
tREMPRE
tRECPRE
tWCLR
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register 0.22
Asynchronous Preset Minimum Pulse Width for the Core Register 0.22
tWPRE
tCKMPWH
tCKMPWL
Clock Minimum Pulse Width HIGH for the Core Register
Clock Minimum Pulse Width LOW for the Core Register
0.32
0.36
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.
2-8
Preliminary v1.7
ACTEL [ Actel Corporation ]
