Actel Fusion Mixed-Signal FPGAs
Data
CLK
Out
Data
Out
D
Q
D
Q
En
DFN1
DFN1E1
CLK
PRE
Data
Out
Data
Out
Q
D
D
Q
En
DFN1C1
DFI1E1P1
CLK
CLK
CLR
Figure 2-5 • Sample of Sequential Cells
t
t
CKMPWH CKMPWL
50%
50%
50%
50%
50%
50%
50%
CLK
t
HD
t
SUD
50%
50%
t
Data
EN
0
t
50%
WPRE
RECPRE
t
REMPRE
t
HE
50%
50%
50%
PRE
CLR
Out
t
SUE
t
RECCLR
t
t
WCLR
REMCLR
50%
50%
50%
t
PRE2Q
t
CLR2Q
50%
50%
50%
t
CLKQ
Figure 2-6 • Sequential Timing Model and Waveforms
Preliminary v1.7
2-7