Fusion Device Family Overview
Advanced Architecture
The proprietary Fusion architecture provides granularity comparable to standard-cell ASICs. The
Fusion device consists of several distinct and programmable architectural features, including the
following (Figure 1-1 on page 1-5):
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Embedded memories
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Flash memory blocks
FlashROM
SRAM and FIFO
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Clocking resources
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PLL and CCC
RC oscillator
Crystal oscillator
No-Glitch MUX (NGMUX)
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Digital I/Os with advanced I/O standards
FPGA VersaTiles
Analog components
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ADC
Analog I/Os supporting voltage, current, and temperature monitoring
1.5 V on-board voltage regulator
Real-time counter
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic lookup table (LUT) equivalent or a D-flip-flop or latch (with or without enable) by
programming the appropriate flash switch interconnections. This versatility allows efficient use of
the FPGA fabric. The VersaTile capability is unique to the Actel families of flash-based FPGAs.
VersaTiles and larger functions are connected with any of the four levels of routing hierarchy. Flash
switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect
programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid (3.3 V) single-voltage
programming of Fusion devices via an IEEE 1532 JTAG interface.
Unprecedented Integration
Integrated Analog Blocks and Analog I/Os
Fusion devices offer robust and flexible analog mixed-signal capability in addition to the high-
performance flash FPGA fabric and flash memory block. The many built-in analog peripherals
include a configurable 32:1 input analog MUX, up to 10 independent MOSFET gate driver outputs,
and a configurable ADC. The ADC supports 8-, 10-, and 12-bit modes of operation with a
cumulative sample rate up to 600 k samples per second (ksps), differential nonlinearity (DNL) < 1.0
LSB, and Total Unadjusted Error (TUE) of 0.72 LSB in 10-bit mode. The TUE is used for
characterization of the conversion error and includes errors from all sources, such as offset and
linearity. Internal bandgap circuitry offers 1% voltage reference accuracy with the flexibility of
utilizing an external reference voltage. The ADC channel sampling sequence and sampling rate are
programmable and implemented in the FPGA logic using Designer and Libero IDE software tool
support.
Two channels of the 32-channel ADCMUX are dedicated. Channel 0 is connected internally to VCC
and can be used to monitor core power supply. Channel 31 is connected to an internal temperature
diode which can be used to monitor device temperature. The 30 remaining channels can be
connected to external analog signals. The exact number of I/Os available for external connection
signals is device-dependent (refer to the "Fusion Family" table on page I for details).
1-4
Preliminary v1.7
ACTEL [ Actel Corporation ]
