欢迎访问ic37.com |
会员登录 免费注册
发布采购

AFS090-1FGG256I 参数 Datasheet PDF下载

AFS090-1FGG256I图片预览
型号: AFS090-1FGG256I
PDF下载: 下载PDF文件 查看货源
内容描述: Actel的Fusion混合信号FPGA [Actel Fusion Mixed-Signal FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 318 页 / 10484 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号AFS090-1FGG256I的Datasheet PDF文件第6页浏览型号AFS090-1FGG256I的Datasheet PDF文件第7页浏览型号AFS090-1FGG256I的Datasheet PDF文件第8页浏览型号AFS090-1FGG256I的Datasheet PDF文件第9页浏览型号AFS090-1FGG256I的Datasheet PDF文件第11页浏览型号AFS090-1FGG256I的Datasheet PDF文件第12页浏览型号AFS090-1FGG256I的Datasheet PDF文件第13页浏览型号AFS090-1FGG256I的Datasheet PDF文件第14页  
Fusion Device Family Overview  
flash operation without wait states. The memory block is organized in pages and sectors. Each  
page has 128 bytes, with 33 pages comprising one sector and 64 sectors per block. The flash block  
can support multiple partitions. The only constraint on size is that partition boundaries must  
coincide with page boundaries. The flexibility and granularity enable many use models and allow  
added granularity in programming updates.  
Fusion devices support two methods of external access to the flash memory blocks. The first  
method is a serial interface that features a built-in JTAG-compliant port, which allows in-system  
programmability during user or monitor/test modes. This serial interface supports programming of  
an AES-encrypted stream. Secure data can be passed through the JTAG interface, decrypted, and  
then programmed in the flash block. The second method is a soft parallel interface.  
FPGA logic or an on-chip soft microprocessor can access flash memory through the parallel  
interface. Since the flash parallel interface is implemented in the FPGA fabric, it can potentially be  
customized to meet special user requirements. For more information, refer to the CoreCFI  
Handbook. The flash memory parallel interface provides configurable byte-wide (×8), word-wide  
(×16), or dual-word-wide (×32) data port options. Through the programmable flash parallel  
interface, the on-chip and off-chip memories can be cascaded for wider or deeper configurations.  
The flash memory has built-in security. The user can configure either the entire flash block or the  
small blocks to prevent unintentional or intrusive attempts to change or destroy the storage  
contents. Each on-chip flash memory block has a dedicated controller, enabling each block to  
operate independently.  
The flash block logic consists of the following sub-blocks:  
Flash block – Contains all stored data. The flash block contains 64 sectors and each sector  
contains 33 pages of data.  
Page Buffer – Contains the contents of the current page being modified. A page contains 8  
blocks of data.  
Block Buffer – Contains the contents of the last block accessed. A block contains 128 data  
bits.  
ECC Logic – The flash memory stores error correction information with each block to  
perform single-bit error correction and double-bit error detection on all data blocks.  
User Nonvolatile FlashROM  
In addition to the flash blocks, Actel Fusion devices have 1 kbit of user-accessible, nonvolatile  
FlashROM on-chip. The FlashROM is organized as 8×128-bit pages. The FlashROM can be used in  
diverse system applications:  
Internet protocol addressing (wireless or fixed)  
System calibration settings  
Device serialization and/or inventory control  
Subscription-based business models (for example, set-top boxes)  
Secure key storage for secure communications algorithms  
Asset management/tracking  
Date stamping  
Version management  
The FlashROM is written using the standard IEEE 1532 JTAG programming interface. Pages can be  
individually programmed (erased and written). On-chip AES decryption can be used selectively over  
public networks to securely load data such as security keys stored in the FlashROM for a user  
design.  
The FlashROM can be programmed (erased and written) via the JTAG programming interface, and  
its contents can be read back either through the JTAG programming interface or via direct FPGA  
core addressing.  
The FlashPoint tool in the Actel Fusion development software solutions, Libero IDE and Designer,  
has extensive support for flash memory blocks and FlashROM. One such feature is auto-generation  
of sequential programming files for applications requiring a unique serial number in each part.  
Another feature allows the inclusion of static data for system version control. Data for the  
FlashROM can be generated quickly and easily using the Actel Libero IDE and Designer software  
1-6  
Preliminary v1.7