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AFS090-1FGG256I 参数 Datasheet PDF下载

AFS090-1FGG256I图片预览
型号: AFS090-1FGG256I
PDF下载: 下载PDF文件 查看货源
内容描述: Actel的Fusion混合信号FPGA [Actel Fusion Mixed-Signal FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 318 页 / 10484 K
品牌: ACTEL [ Actel Corporation ]
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Actel Fusion Mixed-Signal FPGAs  
Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal.  
FB operations are only accepted in cycles where BUSY is logic 0.  
Write Operation  
Write operations are initiated with the assertion of the WEN signal. Figure 2-34 on page 2-47  
illustrates the multiple Write operations.  
CLK  
WEN  
A0  
D0  
A1  
D1  
A2  
A3 A4  
A5  
D5  
A6  
D6  
ADDR[17:0]  
WD[31:0]  
D2 D3 D4  
DATAWIDTH[1:0]  
PAGELOSSPROTECT  
BUSY  
STATUS[1:0]  
S0  
S1  
S2  
S3  
S4  
S5  
S6  
Figure 2-34 • FB Write Waveform  
When a Write operation is initiated to a page that is currently not in the Page Buffer, the FB control  
logic will issue a BUSY signal to the user interface while the page is loaded from the FB Array into  
the Page Buffer. (Note: The number of clock cycles that the BUSY output is asserted during the load  
of the Page Buffer is variable.) After loading the page into the Page Buffer, the addressed data  
block is loaded from the Page Buffer into the Block Buffer. Subsequent writes to the same block of  
the page will incur no busy cycles. A write to another block in the page will assert BUSY for four  
cycles (five cycles when PIPE is asserted), to allow the data to be written to the Page Buffer and  
have the current block loaded into the Block Buffer.  
Write operations are considered successful as long as the STATUS output is '00'. A non-zero STATUS  
indicates that an error was detected during the operation and the write was not performed. Note  
that the STATUS output is "sticky"; it is unchanged until another operation is started.  
Only one word can be written at a time. Write word width is controlled by the DATAWIDTH bus.  
Users are responsible for keeping track of the contents of the Page Buffer and when to program it  
to the array. Just like a regular RAM, writing to random addresses is possible. Users can write into  
the Page Buffer in any order but will incur additional BUSY cycles. It is not necessary to modify the  
entire Page Buffer before saving it to nonvolatile memory.  
Write errors include the following:  
1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not  
performed.  
2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is  
enabled (STATUS = '11'). The write is not performed.  
Program Operation  
A Program operation is initiated by asserting the PROGRAM signal on the interface. Program  
operations save the contents of the Page Buffer to the FB Array. Due to the technologies inherent  
in the FB, a program operation is a time consuming operation (~8 ms). While the FB is writing the  
data to the array, the BUSY signal will be asserted.  
Preliminary v1.7  
2-47  
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