Device Architecture
Analog-to-Digital Converter Block
At the heart of the Fusion analog system is a programmable Successive Approximation Register
(SAR) ADC. The ADC can support 8-, 10-, or 12-bit modes of operation. In 12-bit mode, the ADC can
resolve 500 ksps. All results are MSB-justified in the ADC. The input to the ADC is a large 32:1
analog input multiplexer. A simplified block diagram of the Analog Quads, analog input
multiplexer, and ADC is shown in Figure 2-79. The ADC offers multiple self-calibrating modes to
ensure consistent high performance both at power-up and during runtime.
VCC (1.5 V)
0
1
Pads
AV0
AC0
AG0
AT0
Analog
Quad 0
These are hardwired
connections within
Analog Quad.
ATRETURN01
AV1
AC1
AG1
AT1
Analog
Quad 1
AV2
AC2
AG2
AT2
Analog
Quad 2
ATRETURN23
AV3
AC3
AG3
AT3
Analog
Quad 3
AV4
AC4
AG4
AT4
Analog
Quad 4
12
Analog MUX
(32 to 1)
ATRETURN45
ADC
AV5
AC5
AG5
AT5
AV6
AC6
AG6
AT6
Analog
Quad 5
Digital Output to FPGA
Analog
Quad 6
ATRETURN67
AV7
AC7
AG7
AT7
Analog
Quad 7
AV8
AC8
AG8
AT8
Analog
Quad 8
ATRETURN89
AV9
AC9
AG9
AT9
Analog
Quad 9
31
Temperature
Monitor
CHNUMBER[4:0]
Internal Diode
Figure 2-79 • ADC Block Diagram
2-100
Preliminary v1.7
ACTEL [ Actel Corporation ]
