Device Architecture
Gate Driver
The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin (Figure 2-74).
Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current
sink or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable
gate drive levels: 1 µA, 3 µA, 10 µA, and 30 µA (Figure 2-75 on page 2-95). The AG also supports a
High Current Drive mode in which it can sink 20 mA; in this mode the switching rate is
approximately 1.3 MHz with 100 ns turn-on time and 600 ns turn-off time. Modeled on an open-
drain-style output, it does not output a voltage level without an appropriate pull-up or pull-down
resistor. If 1 V is forced on the drain, the current sinking/sourcing will exceed the ability of the
transistor, and the device could be damaged.
The AG pad is turned on via the corresponding GDONx pin in the Analog Block macro, where x is
the number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).
Power
Line Side
Load Side
Off-Chip
Rpullup
AV
AC
AG
AT
Voltage
Monitor Block
Current
Monitor Block
Gate
Driver
Temperature
Monitor Block
Pads
On-Chip
Analog Quad
Prescaler
Prescaler
Prescaler
Power
MOSFET
Gate Driver
Digital
Input
Digital
Input
Digital
Input
Current
Monitor / Instr
Amplifier
Temperature
Monitor
To FPGA
(DAVOUTx)
To FPGA
(DACOUTx)
From FPGA
(GDONx)
To FPGA
(DATOUTx)
To Analog MUX
To Analog MUX
To Analog MUX
Figure 2-74 • Gate Driver
The gate-to-source voltage (Vgs) of the external MOSFET is limited to the programmable drive
current times the external pull-up or pull-down resistor value (EQ 2-5).
Vgs ≤ Ig × (Rpullup or Rpulldown
)
EQ 2-5
The rate at which the gate voltage of the external MOSFET slews is determined by the current, Ig,
sourced or sunk by the AG pin and the gate-to-source capacitance, CGS, of the external MOSFET. As
an approximation, the slew rate is given by EQ 2-6.
dv/dt = Ig / CGS
EQ 2-6
2-94
Preliminary v1.7
ACTEL [ Actel Corporation ]
