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A3P250-1FGG144I 参数 Datasheet PDF下载

A3P250-1FGG144I图片预览
型号: A3P250-1FGG144I
PDF下载: 下载PDF文件 查看货源
内容描述: 闪光的ProASIC3系列FPGA [ProASIC3 Flash Family FPGAs]
分类和应用: 现场可编程门阵列可编程逻辑
文件页数/大小: 206 页 / 5922 K
品牌: ACTEL [ Actel Corporation ]
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ProASIC3 Device Family Overview  
Bank 0  
CCC  
RAM Block  
4,608-Bit Dual-Port  
SRAM or FIFO Block  
I/Os  
VersaTile  
RAM Block  
4,608-Bit Dual-Port  
SRAM or FIFO Block  
(A3P600 and A3P1000)  
ISP AES  
Decryption  
User Nonvolatile  
FlashROM  
Charge Pumps  
Bank 2  
Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000)  
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input  
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate  
flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input  
lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the  
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation  
architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.  
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable  
interconnect programming. Maximum core utilization is possible for virtually any design.  
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)  
programming of ProASIC3 devices via an IEEE 1532 JTAG interface.  
VersaTiles  
The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core  
tiles. The ProASIC3 VersaTile supports the following:  
All 3-input logic functions—LUT-3 equivalent  
Latch with clear or set  
D-flip-flop with clear or set  
Enable D-flip-flop with clear or set  
1-4  
v1.0  
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