HiRel FPGAs
1200XL Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Logic Module
I/O Module
tINYL = 1.7 ns
t
IRD2 = 5.2 ns†
tDLH = 6.6 ns
tRD1 = 1.7 ns
tRD2 = 2.5 ns
D
G
Q
tPD = 3.7 ns
t
RD4 = 3.7 ns
tRD8 = 7.0 ns
I/O Module
tDLH = 6.6 ns
Sequential
Logic Module
tINH = 0.0 ns
INSU = 0.4 ns
t
t
INGL = 3.7 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tRD1 = 1.7 ns
t
ENHZ = 7.5 ns
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 5.9 ns
tCO = 3.7 ns
t
SU = 0.4 ns
ARRAY
CLOCKS
tHD = 0.0 ns
tCKH = 7.1 ns
FMAX = 110 MHz
FO = 256
tLCO = 10.7 ns (64 loads, pad-pad)
*Values shown for A1280XL–1 at worst-case military conditions.
† Input module predicted routing delay.
17
ACTEL [ Actel Corporation ]
