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A1280XL-FPGC 参数 Datasheet PDF下载

A1280XL-FPGC图片预览
型号: A1280XL-FPGC
PDF下载: 下载PDF文件 查看货源
内容描述: 集成系列FPGA : 1200XL和3200DX家庭 [Integrator Series FPGAs: 1200XL and 3200DX Families]
分类和应用:
文件页数/大小: 84 页 / 3116 K
品牌: ACTEL [ Actel Corporation ]
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Integrator Series FPGAs: 1200XL and 3200DX Families  
programming algorithms. The structure is highly testable  
because there are no pre-existing connections; therefore,  
temporary connections can be made using pass transistors.  
These temporary connections can isolate individual  
CLKB  
CLKA  
CLKINB  
CLKINA  
antifuses to be programmed and individual circuit  
structures to be tested, which can be done before and after  
programming. For example, all metal tracks can be tested  
for continuity and shorts between adjacent tracks, and the  
functionality of all logic modules can be verified.  
From  
Pads  
S0  
S1  
Internal  
Signal  
CLKMOD  
CLKO(17)  
CLKO(16)  
CLKO(15)  
Clock  
Drivers  
Clock Networks  
Two low-skew, high-fanout clock distribution networks are  
provided in each 3200DX device. These networks are  
referred to as CLK0 and CLK1. Each network has a clock  
module (CLKMOD) that selects the source of the clock  
signal and may be driven as follows:  
CLKO(2)  
CLKO(1)  
1. Externally from the CLKA pad  
2. Externally from the CLKB pad  
3. Internally from the CLKINA input  
4. Internally from the CLKINB input  
Clock Tracks  
The clock modules are located in the top row of I/O  
modules. Clock drivers and a dedicated horizontal clock  
track are located in each horizontal routing channel.  
Figure 7 Clock Networks  
IEEE Standard 1149.1 Boundary Scan Testing (BST)  
The user controls the clock module by selecting one of two  
clock macros from the macro library. The macro CLKBUF is  
used to connect one of the two external clock pins to a clock  
network, and the macro CLKINT is used to connect an  
internally-generated clock signal to a clock network. Since  
both clock networks are identical, the user does not care  
whether CLK0 or CLK1 is being used. The clock input pads  
may also be used as normal I/Os, bypassing the clock  
networks (see Figure 7).  
IEEE Standard 1149.1 defines a four-pin Test Access Port  
(TAP) interface for testing integrated circuits in a system.  
The 3200DX family provides five BST pins: Test Data In  
(TDI), Test Data Out (TDO), Test Clock (TCK), and Test  
Mode Select Test Reset (TRST) (3200DX24A only). Devices  
are configured in a test “chain” where BST data can be  
transmitted serially between devices via TDO-to-TDI  
interconnections. The TMS and TCK signals are shared  
among all devices in the test chain so that all components  
operate in the same state.  
The 3200DX devices which contain SRAM modules (all  
except A3265DX and A32140DX) have four additional  
register control resources, called quadrant clock networks  
(Figure 8 on page 10). Each quadrant clock provides a local,  
high-fanout resource to the contiguous logic modules within  
its quadrant of the device. Quadrant clock signals can  
originate from specific I/O pins or from the internal array  
and can be used as a secondary register clock, register  
clear, or output enable.  
The 3200DX family implements a subset of the IEEE  
Standard 1149.1 BST instruction in addition to a private  
instruction, which allows the use of Actel’s ActionProbe  
facility with BST. Refer to the IEEE Standard 1149.1  
specification for detailed information regarding BST.  
Boundary Scan Circuitry  
The 3200DX boundary scan circuitry consists of a Test  
Access Port (TAP) controller, test instruction register, a  
JPROBE register, a bypass register, and a boundary scan  
register. Figure 9 on page 10 shows a block diagram of the  
3200DX boundary scan circuitry.  
Test Circuitry  
All devices contain Actel’s ActionProbe test circuitry which  
test and debug a design once it is programmed into a device.  
Once a device has been programmed, the ActionProbe test  
circuitry allows the designer to probe any internal node  
during device operation to aid in debugging a design. In  
addition, 3200DX devices contain IEEE Standard 1149.1  
boundary scan test circuitry.  
When a device is operating in BST mode, four I/O pins are  
used for the TDI, TDO, TMS, and TCK signals. An active  
reset (nTRST) pin is not supported; however, the 3200DX  
device contain power-on circuitry that resets the boundary  
scan circuitry upon power-up. Table 1 on page 11  
summarizes the functions of the IEEE 1149.1 BST signals.  
Discontinued – v3.0  
9
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