Integrator Series FPGAs: 1200XL and 3200DX Families
3200DX Timing Model (Logic Functions using Array Clocks)*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
I/O Module
INPY = 1.2 ns
t
tIRD1 = 2.7 ns
Combinatorial
Module
t
DLH = 3.2 ns
tRD1 = 0.3 ns
tRD2 = 0.7 ns
tRD4 = 1.2 ns
D
Q
tPD = 2.1 ns
G
Decode
Module
tINH = 0.0 ns
tINSU = 0.4 ns
tINGO = 2.8 ns
t
RDD = 0.4 ns
I/O Module
tPDD = 2.1 ns
tDLH = 3.2 ns
Sequential
Logic Module
t
RD1 = 0.3 ns
Combin-
D
D
G
Q
Q
atorial
Logic
included
in tSUD
tENHZ = 7.1 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tCO = 2.0 ns
tSUD = 0.3 ns
HD = 0.0 ns
t
GHL= 6.5 ns
t
Array
Clocks
tCKH = 5.3 ns
FMAX = 173 MHz
*Values shown for A3265DX-2 at worst-case commercial conditions.
Discontinued – v3.0
17
ACTEL [ Actel Corporation ]
