ACT™ 2 Family FPGAs
A1225A Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
Output Module Timing
‘–2’ Speed
‘–1’ Speed
Min. Max.
‘Std’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
8.0
10.1
8.9
9.0
11.4
10.0
13.2
8.0
10.6
13.4
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.09
0.16
ns
8.9
10.2
12.7
0.08
0.13
ns
tGHL
G to Pad Low
11.2
0.07
0.12
ns
dTLH
dTHL
Delta Low to High
ns/pF
ns/pF
Delta High to Low
CMOS Output Module Timing1
tDLH
Data to Pad High
Data to Pad Low
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
G to Pad High
10.1
8.4
11.5
9.6
13.5
11.2
11.8
15.5
9.4
ns
ns
tDHL
tENZH
tENZL
tENHZ
tENLZ
tGLH
8.9
10.0
13.2
8.0
ns
11.6
7.1
ns
ns
8.3
9.5
11.1
11.9
14.9
0.16
0.12
ns
8.9
10.2
12.7
0.13
0.10
ns
tGHL
G to Pad Low
11.2
0.12
0.09
ns
dTLH
dTHL
Note:
Delta Low to High
Delta High to Low
ns/pF
ns/pF
1. Delays based on 50 pF loading.
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.
14
v4.0
ACTEL [ Actel Corporation ]
