Integrator Series FPGAs: 1200XL and 3200DX Families
A1240XL Timing Characteristics
(Worst-Case Commercial Conditions, V
= 4.75 V, T = 70°C)
J
CC
‘–3’ Speed
Min. Max.
‘–2’ Speed
Min. Max.
‘–1’ Speed
Min. Max.
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
1
Logic ModulePropagation Delays
t
t
t
t
Single Module
2.6
2.6
2.6
2.6
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
5.0
5.0
5.0
5.0
4.2
4.2
4.2
4.2
ns
ns
ns
ns
PD1
CO
GO
RS
Sequential Clk-to-Q
Latch G-to-Q
Flip-Flop (Latch) Reset-to-Q
2
Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.1
1.3
1.7
2.3
3.4
1.2
1.4
1.9
2.6
3.8
1.4
1.7
2.2
3.0
4.5
2.0
2.4
3.1
4.3
6.4
1.7
2.0
2.6
3.6
5.4
ns
ns
ns
ns
ns
RD1
RD2
RD3
RD4
RD8
3, 4
Sequential Timing Characteristics
t
t
t
t
t
t
t
t
t
t
t
f
Flip-Flop (Latch) Data Input Set-Up
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
Flip-Flop Clock Input Period
0.4
0.0
0.8
0.0
3.4
3.4
6.8
0.0
0.3
0.0
0.3
0.4
0.0
0.9
0.0
3.8
3.8
7.7
0.0
0.4
0.0
0.4
0.5
0.0
1.0
0.0
4.5
4.5
9.1
0.0
0.4
0.0
0.4
0.7
0.0
1.4
0.0
6.4
6.4
13.0
0.0
0.6
0.0
0.6
0.6
0.0
1.2
0.0
5.4
5.4
10.9
0.0
0.5
0.0
0.5
ns
ns
SUD
HD
ns
SUENA
HENA
WCLKA
WASYN
A
ns
ns
ns
ns
Input Buffer Latch Hold
ns
INH
Input Buffer Latch Set-Up
ns
INSU
OUTH
OUTSU
MAX
Output Buffer Latch Hold
ns
Output Buffer Latch Set-Up
ns
Flip-Flop (Latch) Clock Frequency
215
190
160
110
105
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts
(adds) to the internal set-up (hold) time.
5. VCC = 3.0V for 3.3V specifications.
Discontinued – v3.0
31
ACTEL [ Actel Corporation ]
