Integrator Series FPGAs: 1200XL and 3200DX Families
A32140DX Timing Characteristics
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
‘–2 Speed
Min. Max.
3.3V ‘Std’
Speed
‘–1’ Speed
Min. Max.
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
1
Logic Module Propagation Delays
Combinatorial Functions
t
t
Internal Array Module Delay
1.8
1.9
2.3
2.5
2.8
3.0
3.6
3.8
3.2
3.5
ns
ns
PD
Internal Decode Module Delay
2
PDD
Predicted Routing Delays
tRD1
tRD2
tRD3
tRD4
tRD5
tRDD
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
1.0
1.4
1.8
2.2
3.8
0.5
1.3
1.9
2.4
2.9
5.0
0.7
1.6
2.2
2.0
2.8
3.7
4.5
7.7
1.0
1.8
2.5
ns
ns
ns
ns
ns
ns
2.8
3.3
3.4
4.0
5.9
7.0
Decode-to-Output Routing Delay
3, 4
0.78
0.91
Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
2.1
1.8
2.8
2.3
3.3
2.8
4.3
3.6
3.9
3.2
ns
ns
ns
ns
ns
ns
ns
ns
tGO
Latch Gate-to-Output
tSU
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
0.3
0.0
0.4
0.0
0.47
0.0
0.6
0.0
0.55
0.0
tH
tRO
2.1
2.8
3.3
4.3
3.9
tSUENA
tHENA
tWCLKA
tWASYN
0.6
0.0
2.6
0.9
0.0
3.5
1.0
0.0
4.1
1.3
0.0
5.4
1.17
0.0
4.82
Flip-Flop (Latch) Asynchronous Pulse Width
4.1
5.5
6.5
8.4
7.6
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Set-Up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal set-up (hold) time.
44
Discontinued – v3.0
ACTEL [ Actel Corporation ]
