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A1240A-1PL176C 参数 Datasheet PDF下载

A1240A-1PL176C图片预览
型号: A1240A-1PL176C
PDF下载: 下载PDF文件 查看货源
内容描述: ACT2系列FPGA [ACT2 Family FPGAs]
分类和应用:
文件页数/大小: 38 页 / 610 K
品牌: ACTEL [ Actel Corporation ]
 浏览型号A1240A-1PL176C的Datasheet PDF文件第16页浏览型号A1240A-1PL176C的Datasheet PDF文件第17页浏览型号A1240A-1PL176C的Datasheet PDF文件第18页浏览型号A1240A-1PL176C的Datasheet PDF文件第19页浏览型号A1240A-1PL176C的Datasheet PDF文件第21页浏览型号A1240A-1PL176C的Datasheet PDF文件第22页浏览型号A1240A-1PL176C的Datasheet PDF文件第23页浏览型号A1240A-1PL176C的Datasheet PDF文件第24页  
ACT2 Family FPGAs  
A1280A Timing Characteristics (continued)  
(Worst-Case Commercial Conditions)  
Output Module Timing  
‘–2Speed  
Min. Max.  
‘–1Speed  
Min. Max.  
StdSpeed  
Parameter  
Description  
Min.  
Max.  
Units  
TTL Output Module Timing1  
tDLH  
Data to Pad High  
Data to Pad Low  
Enable Pad Z to High  
Enable Pad Z to Low  
Enable Pad High to Z  
Enable Pad Low to Z  
G to Pad High  
8.1  
9.0  
10.6  
13.4  
11.8  
15.5  
9.4  
ns  
tDHL  
10.2  
9.0  
11.4  
10.0  
13.2  
8.0  
ns  
tENZH  
tENZL  
tENHZ  
tENLZ  
tGLH  
ns  
11.8  
7.1  
ns  
ns  
8.4  
9.5  
11.1  
11.9  
14.9  
0.09  
0.16  
ns  
9.0  
10.2  
12.7  
0.08  
0.13  
ns  
tGHL  
G to Pad Low  
11.3  
0.07  
0.12  
ns  
dTLH  
dTHL  
Delta Low to High  
Delta High to Low  
ns/pF  
ns/pF  
CMOS Output Module Timing1  
tDLH  
Data to Pad High  
Data to Pad Low  
Enable Pad Z to High  
Enable Pad Z to Low  
Enable Pad High to Z  
Enable Pad Low to Z  
G to Pad High  
10.3  
8.5  
11.5  
9.6  
13.5  
11.2  
11.8  
15.5  
9.4  
ns  
tDHL  
ns  
tENZH  
tENZL  
tENHZ  
tENLZ  
tGLH  
9.0  
10.0  
13.2  
8.0  
ns  
11.8  
7.1  
ns  
ns  
8.4  
9.5  
11.1  
11.9  
14.9  
0.16  
0.12  
ns  
9.0  
10.2  
12.7  
0.13  
0.10  
ns  
tGHL  
G to Pad Low  
11.3  
0.12  
0.09  
ns  
dTLH  
dTHL  
Note:  
Delta Low to High  
Delta High to Low  
ns/pF  
ns/pF  
1. Delays based on 50 pF loading.  
2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board.  
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v4.0  
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