Integrator Series FPGAs: 1200XL and 3200DX Families
Equivalent Capacitance
fp
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
The power dissipated by a CMOS circuit can be expressed by
fq1
Equation 1
fq2
Power (µW) = CEQ * VCC2 * F
(1)
Fixed Capacitance Values for Actel FPGAs
(pF)
where:
CEQ is the equivalent capacitance expressed in picofarads
(pF).
Table 5.
VCC is power supply in volts (V).
r1
routed_Clk1
106
r2
routed_Clk2
106
Device Type
A1225XL
A1240XL
A3265DX
A1280XL
A32100DX
A32140DX
A32200DX
A32300DX
F is the switching frequency in megahertz (MHz).
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over
a range of frequencies at a fixed value of VCC. Equivalent
capacitance is frequency-independent, so the results may
be used over a wide range of operating conditions.
Equivalent capacitance values are shown below.
134
158
168
178
190
230
285
134
158
168
178
190
230
285
C
Values for Actel FPGAs
EQ
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer Loads (CEQCR
)
5.2
11.6
23.8
3.5
Determining Average Switching Frequency
To determine the switching frequency for a design, the user
must have a detailed understanding of the data input values
to the circuit. The following guidelines represent worst-case
scenarios; they can be generally used to predict the upper
limits of power dissipation.
)
)
)
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic
must be known. Equation 2 shows a piece-wise linear
summation over all components.
Logic Modules (m)
=
80% of
Combinatorial
Modules
Power = VCC2 * [(m x CEQM * fm)Modules
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1
+
+
Inputs Switching (n)
Outputs Switching (p)
=
=
=
# of Inputs/4
# Outputs/4
+
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 (2)
First Routed Array Clock Loads
(q1)
40% of Sequential
Modules
where:
m
n
p
= Number of logic modules switching at frequency fm
= Number of input buffers switching at frequency fn
= Number of output buffers switching at frequency fp
Second Routed Array Clock
Loads (q2)
=
40% of Sequential
Modules
Load Capacitance (CL)
=
=
35 pF
F/10
q1
= Number of clock loads on the first routed array
clock
Average Logic Module Switching
Rate (fm)
q2
= Number of clock loads on the second routed array
clock
Average Input Switching Rate
(fn)
=
=
=
=
F/5
F/10
F
r1
r2
= lFixed capacitance due to first routed array clock
= Fixed capacitance due to second routed array
clock
Average Output Switching Rate
(fp)
Average First Routed Array
Clock Rate (fq1)
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
Average Second Routed Array
Clock Rate (fq2)
F/2
CL
fm
fn
= Output load capacitance in p
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
Discontinued – v3.0
15
ACTEL [ Actel Corporation ]
