Integrator Series FPGAs: 1200XL and 3200DX Families
A32300DX Timing Characteristics (continued)
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
3.3V ‘Std’
Speed
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
Input Module Propagation Delays
t
t
Input Data Pad-to-Y
Input Latch
1.4
2.9
1.7
3.4
1.9
3.8
2.2
4.5
3.1
6.4
2.5
5.2
ns
INPY
INGO
1
Gate-to-Output
ns
ns
ns
ns
1
t
t
t
Input Latch Hold
0.0
0.45
4.4
0.0
0.5
5.2
0.0
0.6
5.9
0.0
0.7
6.9
0.0
1.0
9.8
0.0
0.82
8.1
INH
INSU
ILA
1
Input Latch Set-Up
1
Latch Active Pulse Width
Input Module Predicted Routing Delays
t
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
1.9
2.5
3.3
3.9
5.0
0.6
2.3
2.9
2.6
3.3
4.4
5.2
6.7
0.8
3.0
3.9
5.2
6.1
7.9
0.9
4.2
5.5
7.4
8.7
11.2
1.3
3.5
4.6
ns
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD5
RDD
3.9
6.1
4.6
7.2
6.0
9.2
0.67
1.05
Global Clock Network
t
Input Low to High
FO=32
FO=635
6.4
7.3
7.6
8.6
8.6
9.7
10.1
11.4
14.4
16.2
11.8
13.4
ns
ns
CKH
FO=32
FO=635
6.6
7.1
7.7
8.4
8.8
9.5
10.3
11.2
14.7
16.0
12.1
13.1
ns
ns
t
t
Input High to Low
CKL
FO=32
FO=635
3.0
3.3
3.5
3.8
4.0
4.3
4.7
5.1
6.7
7.2
5.5
6.0
ns
ns
PWH
Minimum Pulse Width High
Minimum Pulse Width Low
Maximum Skew
t
FO=32
FO=635
3.0
3.3
3.8
3.8
4.0
4.3
4.7
5.1
6.7
7.2
5.5
6.0
ns
ns
PWL
FO=32
FO=635
0.6
0.6
0.75
0.75
0.9
0.9
1.0
1.0
1.4
1.4
1.17
1.17
ns
ns
t
t
CKSW
Input Latch External
Set-Up
FO=32
FO=635
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
SUEXT
t
t
f
FO=32
FO=635
2.2
2.7
2.6
3.2
2.9
3.7
3.4
4.3
4.9
6.1
4.0
5.0
ns
ns
HEXT
P
Input Latch External Hold
Minimum Period (1/fmax)
FO=32
FO=635
5.5
6.1
6.9
7.7
7.4
8.2
9.3
10.2
13.2
14.5
10.9
12.0
ns
ns
Maximum Datapath
Frequency
FO=32
FO=635
154
141
142
130
123
113
107
98
75
69
91
83
MHz
MHz
HMAX
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Discontinued – v3.0
53
ACTEL [ Actel Corporation ]
