Integrator Series FPGAs: 1200XL and 3200DX Families
A32300DX Timing Characteristics (continued)
(Worst-Case Commercial Conditions V
= 4.75 V, T = 70°C)
J
CC
3.3V ‘Std’
Speed
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
TTL Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High
3.7
4.4
4.8
5.1
8.3
8.3
4.3
5.4
4.3
5.2
4.9
5.9
5.8
6.9
7.7
8.1
8.2
9.8
ns
ns
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
Data-to-Pad Low
Enable-Pad Z to High
5.6
6.4
7.5
8.8
10.7
11.4
18.5
18.5
9.6
ns
Enable-Pad Z to Low
6.0
6.8
8.0
9.4
ns
Enable-Pad High to Z
9.75
9.75
5.0
11.1
11.1
5.7
13.0
13.0
6.7
15.2
15.2
7.9
ns
Enable-Pad Low to Z
ns
G-to-Pad High
ns
G-to-Pad Low
6.3
7.1
8.4
7.9
12.0
ns
I/O Latch Output Set-Up
I/O Latch Output Hold
0.26
0.0
0.3
0.0
0.34
0.0
0.4
0.0
0.47
0.0
0.6
0.0
ns
ns
LH
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
8.4
9.7
13.9
0.3
11.1
15.7
0.34
0.4
13.1
18.5
0.4
15.4
21.8
0.47
0.58
0.058
18.7
26.5
0.6
ns
LCO
ACO
11.8
0.26
0.32
0.03
ns
d
d
ns/pF
ns/pF
ns
TLH
THL
0.37
0.037
0.5
0.7
t
Hard-Wired Wide-Decode Output
1
0.04
0.05
0.07
WDO
CMOS Output Module Timing
t
t
t
t
t
t
t
t
t
t
t
t
Data-to-Pad High
4.4
3.7
4.8
5.1
8.3
8.3
4.3
5.4
5.2
4.3
5.9
4.9
6.9
5.8
8.1
7.7
8.2
9.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DLH
DHL
ENZH
ENZL
ENHZ
ENLZ
GLH
GHL
LSU
Data-to-Pad Low
Enable-Pad Z to High
5.6
6.4
7.5
8.8
10.7
11.4
18.5
18.5
9.6
Enable-Pad Z to Low
6.0
6.8
8.0
9.4
Enable-Pad High to Z
9.75
9.75
5.0
11.1
11.1
5.7
13.0
13.0
6.7
15.2
15.2
7.9
Enable-Pad Low to Z
G-to-Pad High
G-to-Pad Low
6.3
7.1
8.4
9.9
12.0
I/O Latch Set-Up
0.26
0.0
0.3
0.0
0.34
0.0
0.4
0.0
0.47
0.0
0.6
0.0
I/O Latch Hold
LH
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
Capacitive Loading, Low to High
Capacitive Loading, High to Low
Hard-Wired Wide-Decode Output
9.9
11.6
16.4
0.37
0.3
13.2
18.5
0.4
15.5
21.8
0.5
17.6
25.6
0.6
22.3
31.2
LCO
ACO
13.9
0.32
0.26
0.03
d
d
0.10 ns/pF
0.09 ns/pF
TLH
THL
0.3
0.4
0.5
t
0.037
0.04
0.05
0.06
0.09
ns
WDO
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
54
Discontinued – v3.0
ACTEL [ Actel Corporation ]
