A C T 1 T i m i n g M o d u l e *
Input Delay
Internal Delays
Predicted
Routing
Delays
Output Delay
I/O Module
I/O Module
Logic Module
t
= 3.1 ns
INYL
t
t
= 1.4 ns
IRD2
t
= 6.7 ns
DLH
t
= 0.9 ns
= 3.1 ns
= 6.6 ns
t
t
t
= 0.9 ns
IRD1
RD1
t
t
= 2.9 ns
= 2.9 ns
PD
CO
t
= 11.6 ns
= 1.4 ns
= 3.1 ns
= 6.6 ns
ENHZ
RD2
IRD4
t
IRD8
RD4
t
RD8
ARRAY
CLOCK
t
= 5.6 ns
FO = 128
CKH
F
= 70 MHz
MAX
* Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions.
P r e d i c t a b l e P e r f o r m a n c e : T i g h t D e l a y
D i s t r i b u t i o n s
T i m i n g C h a r a c t e r i s t i c s
Timing characteristics for ACT 1 devices fall into three
categories: family dependent, device dependent, and design
dependent. The input and output buffer characteristics are
common to all ACT 1 family members. Internal routing delays
are device dependent. Design dependency means actual delays
are not determined until after placement and routing of the
user design is complete. Delay values may then be determined
by using the DirectTime Analyzer utility or performing
simulation with post-layout delays.
Propagation delay between logic modules depends on the
resistive and capacitive loading of the routing tracks, the
interconnect elements, and the module inputs being driven.
Propagation delay increases as the length of routing tracks,
the number of interconnect elements, or the number of
inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout (number of
loads) driven by a module. Higher fanout usually requires
some paths to have longer routing tracks.
C r it ic a l N e t s a n d T y p ic a l N e t s
Propagation delays are expressed only for typical nets, which
are used for initial design performance evaluation. Critical
net delays can then be applied to the most time-critical paths.
Critical nets are determined by net property assignment prior
to placement and routing. Up to 6% of the nets in a design may
be designated as critical, while 90% of the nets in a design are
typical.
The ACT 1 family delivers a very tight fanout delay
distribution. This tight distribution is achieved in two ways: by
decreasing the delay of the interconnect elements and by
decreasing the number of interconnect elements per path.
Actel’s patented PLICE antifuse offers a very low
resistive/capacitive interconnect. The ACT 1 family’s
antifuses, fabricated in 1.0 micron lithography, offer nominal
levels of 200 ohms resistance and 7.5 femtofarad (fF)
capacitance per antifuse.
Lo n g T r a c k s
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns, or
modules. Long tracks employ three and sometimes four
antifuse connections. This increases capacitance and
resistance, resulting in longer net delays for macros
connected to long tracks. Typically, up to 6% of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 5 ns to 10 ns delay. This additional delay is
represented statistically in higher fanout (FO=8) routing
delays in the data sheet specifications section.
The ACT 1 fanout distribution is also tight due to the low
number of antifuses required for each interconnect path. The
ACT 1 family’s proprietary architecture limits the number of
antifuses per path to a maximum of four, with 90% of
interconnects using two antifuses.
1 -2 9 2
ACTEL [ Actel Corporation ]
