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5962-9096501MZX 参数 Datasheet PDF下载

5962-9096501MZX图片预览
型号: 5962-9096501MZX
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 547 CLBs, 2000 Gates, CMOS, CQCC84, CERAMIC, QCC-84]
分类和应用: 可编程逻辑
文件页数/大小: 25 页 / 216 K
品牌: ACTEL [ Actel Corporation ]
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TABLE IB. SEP test limits. 1/ 3/  
Symbol  
Characteristics  
Upset Mode  
Conditions  
Bias  
Effective LET  
no upset  
Saturated  
X-section  
VDD  
=
(MeV-cm2/mg)  
SEL  
SEU  
Single event latchup  
Single event upset  
all  
C-Latch  
1 MHz Clock 2/  
all  
5.5 V  
4.5 V  
5.0 V  
5.5 V  
>84  
>8 3/  
18.8  
>40  
N/A  
1.5 x 10-6 cm2/bit  
2.5 x 10-7 cm2/device  
N/A  
-55°CTC125°C  
-55°CTC125°C  
TA = +25°C  
SEDR  
4/  
Single event dielectric  
(antifuse) rupture  
-55°CTC125°C  
Notes:  
1/. Verification test per TRB approved test plan.  
2/. Clock upset causes upset in the clocked flip-flops, its rate is proportional to the clock frequency and can be computed  
using the following;  
3x10-8 upset/device-day ;  
1 MHz  
f x  
Where f is the clock frequency of interest and 3 x 10-8 (upset/device-day) is the computed rate from the SEU testing data.  
3/. Threshold LET at 1% saturated X-section is 13, and at 10%, saturated X-section is 25.  
4/. Tested at worst case that ions have perpendicular incidence.  
4.2.2 Additional criteria for device classes Q and V.  
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the  
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained  
under document revision level control of the device manufacturer's Technology Review Board (TRB) in  
accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request.  
The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with  
the intent specified in method 1015 of MIL-STD-883.  
b. Interim and final electrical test parameters shall be as specified in table IIA herein.  
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in appendix B of  
MIL-PRF-38535.  
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in  
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups  
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).  
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-  
38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits  
alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-STD-883  
(see 3.1 herein) and as specified herein. Inspections to be performed for device class M shall be those specified in method  
5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).  
4.4.1 Group A inspection.  
a. Tests shall be as specified in table IIA herein.  
b. Subgroups 5 and 6 of table IA of method 5005 of MIL-STD-883 shall be omitted.  
c. Subgroup 4 (C and C measurements) shall be measured only for initial qualification and after any process or design  
I
O
changes which may affect input or output capacitance. A sample size of 5 devices with no failures, and all input and  
output terminals shall be required.  
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may  
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document  
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon  
request. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturer's  
TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon  
request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive.  
Information contained in JEDEC Standard EIA/JESD78 may be used for reference.  
SIZE  
STANDARD  
5962-90965  
A
MICROCIRCUIT DRAWING  
DEFENSE SUPPLY CENTER COLUMBUS  
COLUMBUS, OHIO 43218-3990  
REVISION LEVEL  
G
SHEET  
7
DSCC FORM 2234  
APR 97  
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