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5962-0422104QUC 参数 Datasheet PDF下载

5962-0422104QUC图片预览
型号: 5962-0422104QUC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 2000000 Gates, 32256-Cell, CMOS, CQFP256, CERAMIC, QFP-256]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX B  
B.4 VERIFICATION  
B.4.1 Screening test for class V and class Y . In addition to the screening tests specified in the main body of this specification, the  
screening tests specified below shall be performed, unless prior approval for deletion or modification is given by the qualifying  
activity.  
a. Nondestructive bond pull (NDBP) in accordance with TM 2023 of MIL-STD-883, or approved alternate verified during  
validation, on each interconnect bond. An alternate method, if necessary, shall consider a 100 percent visual inspection of  
the elements to be bonded (e.g., bond pads and posts) prior to the bonding operation, as one part of an overall alternate  
method. For flip chip package devices, Nondestructive bond pull (NDBP) test is not required.  
b. Particle impact noise detection (PIND) in accordance with TM 2020, condition A of MIL-STD-883 on each device. For  
devices without a cavity such as class Y or flip chip devices with underfill, Particle impact noise detection (PIND) test is not  
applicable.  
c. Radiograph inspection in accordance with TM 2012 of MIL-STD-883 on each device. Only one view is required  
for flat packages and leadless chip carriers having lead terminal metal on four sides.  
d. For flip chip technology C-SAM inspection is required.  
i) C-SAM inspection shall be performed on each flip chip device in accordance with TM 2030 of MIL-STD-883.  
ii) C-SAM test shall be performed on each device when a heat sink or lid is attached directly to the back side of the  
flip chip die in accordance with TM 2030 of MIL-STD-883.  
e. Seal test (TM 1014) is not required for class Y non-hermetic devices.  
f. Burn-in test in accordance with TM 1015 of MIL-STD-883 shall be conducted on each device for 240 total hours at +125°C.  
For a specific device type, the burn-in duration may be reduced from 240 to 160 hours if three consecutive production lots  
of identical parts, from three different wafer lots pass percent defective allowable (PDA) requirements after completing 240  
hours of burn-in. Sufficient analysis (not necessarily failure analysis) of all failures occurring during the run of the three  
consecutive burn-in lots shall not reveal a systematic pattern of failure indicating an inherent reliability problem which would  
require that burn-in be performed for a longer time. Other burn-in conditions may be considered by a class level S  
validation team. The manufacturer's burn-in procedures shall contain corrective action plans, approved by the validation  
team, for dealing with lot failures. PDA shall be in accordance with table IA as specified herein or TM 5004 of MIL-STD-  
883 for class level S. Static burn-in may be substituted for high temperature reverse bias burn-in based on device  
technology and must be approved by the QA. Moreover, burn-in test time-temperature regression table I of TM 1015 of  
MIL-STD-883 can be used for determination of reverse bias burn-in time and temperature.  
g. Wafer lot acceptance testing in accordance with TM 5007 of MIL-STD-883 or an alternative which meets the minimum  
requirements of TM 5007 shall be conducted on each wafer lot producing class V or S devices (see H.3.2.1.4).  
B.4.2 Screening for solder termination microcircuits of class V and class Y . In addition to the screening tests specified in the main  
body of this specification for solder terminated microcircuits, the screening tests specified below shall be performed, unless prior  
approval for deletion or modification is given by the qualifying activity.  
B.4.2.1 Ball grid array (BGA) microcircuits . For BGA microcircuits post-assembly screening burn-in test may be performed before  
the solder balls have been attached to the package. Electrical test shall be performed across the full military temperature range after  
attachment of the solder balls on the package.  
B.4.2.2 Column grid array (CGA) microcircuits . For CGA microcircuits post-assembly screening (including electrical test and  
burn-in) may be performed before the solder columns have been attached to the package. Electrical test shall be performed across  
the full military temperature range before attachment of the solder columns on the package.  
After column attach, electrical test shall be performed at 25°C (Group A, subgroup 1) as a minimum to verify that no  
electrical/mechanical damage has been introduced due to the column attach process, and visual inspection shall be performed  
according to TM 2009 of MIL-STD-883.  
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