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5962-0151801QYC 参数 Datasheet PDF下载

5962-0151801QYC图片预览
型号: 5962-0151801QYC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 32000 Gates, 206MHz, 2880-Cell, CMOS, CQFP208, CERAMIC, QFP-208]
分类和应用: 可编程逻辑
文件页数/大小: 217 页 / 1554 K
品牌: ACTEL [ Actel Corporation ]
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MIL-PRF-38535K  
APPENDIX A  
A.3.5.6.3.2 Lead finish. The finish system on all external leads or terminals shall conform to one of the  
combinations listed in table A-II, and to the thickness and composition requirements of table A-III. The finish system  
shall also conform to the requirements of A.3.5.6.3.4 and A.3.5.6.3.5, where applicable.  
A.3.5.6.3.3 Package element (other than lead or terminal) finish. External metallic package elements other than  
leads and terminals (e.g., lids, covers, bases, and seal rings) shall meet the applicable environmental requirements  
without additional finishing of the base materials or else they shall be finished so they meet those requirements using  
a finish system conforming to one of the combinations listed in table A-IV, and conforming to the thickness and  
composition requirements of table A-III. The finish system shall also conform to the requirements of A.3.5.6.3.4 and  
A.3.5.6.3.5, where applicable.  
A.3.5.6.3.4 Hot solder dip. The hot solder dip shall be homogeneous and shall be applied as follows:  
a. All outlines with hot solder dip over compliant coating. The hot solder dip shall extend beyond the  
effective seating plane. If the seating plane is not defined, the hot solder dip shall extend to within  
0.040 inch (1.02 mm) of the lead/package interface and is bound by the lead/package interface and shall  
not touch interface of lead/package body. For dual in line type termination forms (through hole and  
surface mount), the plane of the two longest lead/package interfaces will define this bound. For leadless  
chip carrier devices, the hot solder dip shall cover a minimum of 95 percent of the metallized side  
castellation or notch and metallized areas above and below the notch, except the index feature, if not  
connected to the castellation. Terminal area intended for device mounting shall be completely covered.  
For top brazed and bottom brazed flat pack packages, the hot solder dip shall extend to within 0.070 inch  
(1.78 mm) of the lead/package interface and is bound by the lead/package interface.  
b. All outlines with hot solder dip over base metal or noncompliant coating. The solder shall extend to the  
glass seal or point of emergence of the metallized contact or lead through the package wall. If solder is  
applied up to the seal, a hermeticity test (TM 1014 of MIL-STD-883, and table IA footnote 20/ herein  
shall subsequently be performed and passed. For leadless chip carrier devices, the hot solder dip shall  
completely cover the metallized side castellation or notch and metallized areas above and below the  
notch, except the index feature if not connected to the castellation.  
FIGURE A-1. Solder dipping area when seating plane is not defined .  
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