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5962-0422102QZA 参数 Datasheet PDF下载

5962-0422102QZA图片预览
型号: 5962-0422102QZA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 32256-Cell, CMOS, CBGA624,]
分类和应用: 可编程逻辑
文件页数/大小: 52 页 / 373 K
品牌: ACTEL [ Actel Corporation ]
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9/ N/C is No-Connect pin, it is not connected to circuitry within the device, and can be driven to any voltage or be left floating  
with no effect on the operation of the device.  
10/ I/O Customizations: By utilizing manufacturer’s Designer software (see 6.7 herein), the following I/O features can be  
customized:  
Bank-Wide Programmable Input Delays: A five-bit programmable input delay element is associated with each I/O. The  
value of this delay is set on a bank-wide basis. It is optional for each input buffer within the bank (i.e. the user can enable or  
disable the delay element for the I/O). The default setting for this property can be set in Manufacturer’s Designer software.  
When the input buffer drives a register within the I/O, the delay element is activated by default to ensure a zero hold-time.  
When the input buffer does not drive a register, the delay element is deactivated to provide higher performance.  
Slew-Rate and Drive Strength for LVTTL Output Buffer: By using Manufacturer’s Designer software, the slew-rate value for  
the LVTTL output buffer can be programmed and can be set to either slow or fast. The drive strength value for LVTTL  
output buffer can also be programmed to four different drive strength values (8mA, 12mA, 16mA, or 24mA).  
Other I/O types and features: Differential I/O standards, voltage-referenced I/O standards, Double Data Rate (DDR),  
access to I/O registers, using weak pull-up and pull-down resistors can be instantiated through using I/O macros in  
manufacturer’s Designer software.  
FIGURE 2. Terminal connections – Continued.  
SIZE  
STANDARD  
5962-04221  
A
MICROCIRCUIT DRAWING  
DEFENSE SUPPLY CENTER COLUMBUS  
COLUMBUS, OHIO 43218-3990  
REVISION LEVEL  
SHEET  
C
43  
DSCC FORM 2234  
APR 97  
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