1/ IO pin naming scheme shows which bank an I/O belongs, and the pairing and pin polarity for differential I/Os:
“IOXXYB FG”: XX(X)* is the I/O pair number, starting with “00”; Y is “P” = Positive Pin or “N” = Negative pin;
is the I/O bank ID (0 – 7);
Note: * the third X denotes I/O numbers greater than 99.
FG can be ignored (not used)
a slash / provides a division of the IO naming scheme as indicated below
“IOXXYB FG” / Special_Function_Name”: This pin can be configured as an I/O pin or a special function pin.
2/ HCLKA/B/C/D are the clock inputs for sequential modules, they are directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven. HCLKE/F/G/H are the clock inputs for clock distribution networks, they
are buffered prior to clocking the R-cells. All clock pins (HCLKA/B/C/D, CLKE/F/G/H) are compatible with all supported I/O
standards, when they are used with single-ended I/O standard, they must be tied to the P-pads of the clock package pins,
and the N-pads can be used as user I/Os. When any of the HCLKA/B/C/D pins are not used either as clock or I/O pins, they
shall be tied to Ground. When any of the CLKE/F/G/H pins are not used either as clock or I/O pins, they shall be tied to a
known state.
3/ VCCIBX is the supply voltage for I/O, BX is the I/O bank ID (0-7).
Unused I/O banks may be tied to GND or can be tied to other used I/O banks within the same device.
4/ VCCDA is the supply voltage for the I/O differential amplifier, JTAG and Probe interfaces. VCCDA is either 3.3V or 2.5V, and
must be 3.3V when voltage-referenced and/or differential IO are used. Additionally, VCCDA must be greater than or equal to
any VCCI voltages (i.e. VCCDA VCCIBX
)
5/ JTAG interface (include TMS, TDI, TCK, TRST, and TDO pins) is compliant with the IEEE 1149.1 standard, except for the
device ID length, which is 33 bits.
6/ Probe pins (PRA, PRB, PRC, PRD) are used to bring out up to four individual signals inside the device without disturbing
normal device operation to allow real time diagnostics. The probe circuitry is accessed and controlled via manufacturer’s
Silicon Explorer II tool and communicates with the device via the JTAG port.
7/ JTAG and Probe pins should be configured for flight as below:
Pin Name
TCK
Configurations
Can be hardwired to VCCDA or Ground, or can be driven to VCCDA or Ground, and
TCK pin must not be left un-terminated
TDO
Must be left un-connected
Can be hardwired or driven to VCCDA, or can be left unconnected (equipped with 10k internal
pull-up resistor)
TDI, TMS
Must be hardwired to ground (Optional 10k internal pull-up resistor can be set by user at
programming. Care should be exercised when using this option in combination with an external
tie-off to ground)
TRST
PRA, PRB
PRC, PRD
Must be left unconnected
8/ VPUMP is used to access an external charge pump by bypassing internal charge pump to reduce power consumption. When
PUMP voltage level is set to 3.3V, the device will use VPUMP voltage as the charge pump voltage and the internal charge
V
pump will be turned off. Adequate voltage regulation (i.e., high drive, low output impedance, and good decoupling) shall be
used for VPUMP shall be directly tied or through a 1kΩ resistor to the Ground.
FIGURE 2. Terminal connections – Continued.
SIZE
STANDARD
5962-04221
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
C
42
DSCC FORM 2234
APR 97
ACTEL [ Actel Corporation ]
