Core1553BBC MIL-STD-1553B Bus Controller
General Description
The Core1553BBC provides a complete, MIL-STD-1553B
Bus Controller (BC). A typical system implementation
using the Core1553BBC is shown in
Core1553BBC reads message descriptor blocks from the
memory and generates messages that are transmitted on
the 1553B bus. Data words are read from the memory
and transmitted on the 1553B bus. Data received is
written to the memory. The core can be configured
directly to connect to synchronous or asynchronous
memory devices.
The core consists of five main blocks: the 1553B encoder,
the 1553B decoder, a protocol controller block, a CPU
interface, and a backend interface (Figure
2).
Backend
Interface
Memory
BUSAINEN
BUSAINP
BUSAINN
BUSAOUTINH
BUSAOUTP
BUSAOUTN
RCVSTBA
RXDAIN
RXDAIN
TXINHA
TXDAIN
TXDAIN
Transceiver
(Not Included)
RCVSTBA
RXDBIN
RXDBIN
TXINHA
TXDBIN
TXDBIN
Glue
Logic
CPU
CPU
Interface
Encoder
Decoder
BUSBINEN
BUSBINP
BUSBIN
BUSAOUTINH
BUSBOUTP
BUSBOUTN
Core1553BBC
Actel FPGA
Figure 1 •
Typical Core1553BBC System
BusA
Protocol
Controller
BusB
Backend
Interface
CPU
Interface
and
Registers
Core1553BBC
Memory
64K*16
Figure 2 •
Core1553BBC BC Block Diagram
2
v4.0
ACTEL [ Actel Corporation ]
