Core1553BBC MIL-STD-1553B Bus Controller
Backend Interface
The backend interface supports both synchronous operation and asynchronous operation to backend devices.
Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows
connection to standard external memory devices.
Table 5 •
Backend Signals
Name
MEMREQn
Type Description
Out
Memory Request (active low) output. The BC holds MEMREQn active if it requires additional memory
access cycles to take place immediately after the current memory cycle. This occurs during the inter-
message gap.
Memory Grant (active low) input. This input should be synchronous to CLK and needs to meet the
internal register setup time. This input may be held low if the core has continuous access to the RAM.
Memory Write (active low). When MEMWRn[1] is '0,' D[15:8] is written. When MEMWRn[0] is '0,' D[7:0]
is written.
Synchronous mode: This output indicates that data will be written on the rising clock edge. If
MEMWAITn is asserted, the MEMWRn pulse will be extended until MEMWAITn becomes inactive.
Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by
the MEMWAITn input. The address and data are valid one clock cycle before MEMWRn is active and held
for one clock cycle after MEMWRn goes inactive.
Memory Read (active low)
Synchronous mode: This output indicates that data is read on the next rising clock edge. If MEMWAITn is
active, then the data will be sampled on the rising clock edge on which MEMWAITn becomes inactive.
This signal is intended as the read signal for synchronous RAMS.
Asynchronous mode: This output will be low for a minimum of one clock period and can be extended by
the MEMWAITn input. The address is valid one clock cycle before MEMRDn is active and held for one
clock cycle after MEMRDn goes inactive. The data is sampled as MEMRDn goes high.
Memory Chip Select (active low). This output has the same timing as MEMADDR.
Memory Wait (active low) indicates that the backend is not ready, and the core should extend the read or
write strobe period. This input should be synchronous to CLK and needs to meet the internal register
setup time. It can be permanently held high.
Memory address output
Memory data output
Memory data input
Control signal enable (active high). This signal is high when the core is requesting the memory bus and
has been granted control. It is intended to enable any tristate drivers that may be implemented on the
memory control and address lines.
Data bus enable (active high). This signal is high when the core is requesting the memory bus has been
granted control and is waiting to write data. It is intended to enable any bidirectional drivers that may be
implemented on the memory data bus.
MEMGNTn
MEMWRn[1:0]
In
Out
MEMRDn
Out
MEMCSn
MEMWAITn
Out
In
MEMADDR[15:0]
MEMDOUT[15:0]
MEMDIN[15:0]
MEMCEN
Out
Out
In
Out
MEMDEN
Out
The backend interface must allow the bus controller
access to the memory when requested. The memory
access time from MEMREQn low to completion of the
access cycle MEMRDn and MEMWRn high varies
depending on the BC setup. When the CPU is allowed to
access the memory through the bus controller
(CPUMEMEN active), the memory access time is reduced
If the backend fails to allow the bus controller access to
the memory in the required time, the bus controller will
assert its MEMFAIL output and stop operation.
8
v4.0
ACTEL [ Actel Corporation ]
