Core1553BBC MIL-STD-1553B Bus Controller
Table 9 • Setup Register (Continued)
Bits
Name
Type
Reset Function
3:2
RESPTIME
RW
01
Sets the maximum time that the BC will wait for an RT to respond
00: 12µs
01: 16µs
10: 20µs
11: 24µs
1:0
Reserved
R
00
Reserved, return 00
Table 10 • Control Register
Bits
Name
Type
Function
3
ASYNC
W
Writing a '1' causes the bus controller to jump to process the asynchronous instruction list pointed to
by the ASYNCPTR register at the end of the current message. When a RETAS instruction is found, the
bus controller returns to the original instruction list. An ASYNC instruction can be issued while the
bus controller is both active and inactive.
2
ABORT
W
Writing a '1' stops the bus controller immediately; both normal and asynchronous message operation
will be aborted.
1
0
STOP
W
W
Writing a '1' stops the bus controller at the end of the current message.
START
Writing a '1' starts the bus controller. The bus controller cannot be started when an asynchronous
message is active.
Table 11 • Status Register
Bits
Name
Type
Function
15:8
VERSION
R
Indicates the Core1553BBC code revision
Core release notes provide latest version numbers.
7:6
5
Reserved
LOOPFAIL
FRAMEOK
R
R
R
Reserved, set to 00
Indicates that a loopback failure occurred in the current frame
4
Indicates that all the messages in the current frame have completed successfully and no system
action is required
3
2
FLAG
R
R
Indicates the value of the flag condition stored by the STOREFLAG instruction
ASYNC
Asynchronous message requested or in progress. This bit is cleared by the RETAS instruction. When it
is active, the bus controller cannot be started.
1
0
BUSINUSE
ACTIVE
R
R
Indicates which bus is in use
0: Bus A
1: Bus B
BC is Active
v4.0
11
ACTEL [ Actel Corporation ]
