Core1553BBC MIL-STD-1553B Bus Controller
Table 8 • Bus Controller Registers
Address
Name
Type
Size
Function
110
STACKPTR
RW
[15:0]
BC stack pointer
This is the internal stack pointer register; it is used for the CALL and
RETURN instructions. When the bus controller is started, the STACKPTR
is set to FFFF. The upper eight bits are fixed to FF, and the lower eight
bits will count down and up. This allows up to 255 addresses to be
stored in the stack memory.
111
INTERRUPT
RW
[15:0]
Interrupt Register
Table 9 • Setup Register
Bits
Name
Type
Reset Function
15
FORCEORUN
RW
0
'1': If a BC-RT message with a word count between 1 and 31 is carried out, the BC will
transmit for greater than 680µs. This will cause the transmitter timer to trigger and the
BC to shutdown.
'0': Normal operation
14
CLOCKEN
CLKFREQ
RW
RW
0
Enables the internal CLOCK to count
'0': Internal CLOCK will not count
'1': Internal CLOCK enabled
The clock is automatically enabled by the WAITC instruction.
13:12
01
Tells the core what the external clock frequency is
00: 12 MHz
01: 16 MHz
10: 20 MHz
11: 24 MHz
11
RETRYMODE
WR
0
Sets how the retry system works
'0': Retries on the same bus for the number of times set by the reties setting in the
message block, then on the alternate bus for the number of times set by the alternate
bus reties in the message block.
'1': Reties alternates between the two buses. The total number of retries is the number
of reties plus alternative bus retries as set in the message block.
10
INTENABLE
RW
0
Enables the external interrupt pin
'1': The INTPENDING bit will drive the INTOUT pin
'0': The INTOUT pin is held at a '0'
9
8
AUTOCLOCK
AUTOSTACK
RW
RW
1
1
'1': Sets the CLOCK register to 0000 when the BC is started
'0': The CLOCK register is not reset when the BC is started
'1': Sets the STACKPTR register to FFFF when the BC is started
'0': The STACKPTR register is not reset when the BC is started. This allows the BC to be
restarted when previously stopped.
7:6
5:4
CLKRATE
IMG
RW
RW
00
00
Sets the rate at which the TIMER and CLOCK count
00: 1µs
01: 4µs
10: 8µs
11: 32µs
Sets the default minimum inter-message GAP
00: 4µs
01: 8µs
10: 16µs
11: 32µs
Note: The actual inter-message GAP is a function of the memory access times. Typically,
six memory accesses need to take place in the inter-message gap.
10
v4.0
ACTEL [ Actel Corporation ]
