ACE24C1024
Two-wire Serial EEPROM
Stop Condition:
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Figure 5).
Acknowledge:
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Standby Mode :
The ACE24C1024 features a low-power standby mode which is enabled: (a) upon power-up and (b)
after the receipt of the stop bit and the completion of any internal operations.
Memory Reset :
After an interruption in protocol power loss or system reset, any two-wire part can be protocol reset by following
these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high and then.
3. Create a start condition as SDA is high.
Bus Timing
Figure 2．SCL: Serial Clock, SDA: Serial Data I/O
VER 1.4
6
ACE [ ACE TECHNOLOGY CO., LTD. ]
