AD9512
TIMING CHARACTERISTICS
Table 3.
Parameter
LVPECL
Output Rise Time, t
RP
Output Fall Time, t
FP
PROPAGATION DELAY, t
PECL
, CLK-TO-LVPECL OUT
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, t
SKP 2
OUT1 to OUT2 on Same Part, t
SKP2
OUT0 to OUT2 on Same Part, t
SKP2
All LVPECL OUT Across Multiple Parts, t
SKP_AB 3
Same LVPECL OUT Across Multiple Parts, t
SKP_AB3
LVDS
Min
Typ
Max
Unit
Test Conditions/Comments
Termination = 50 Ω to V
S
− 2 V
Output level 3Dh (3Eh) (3Fh)<3:2> = 10b
20% to 80%, measured differentially
80% to 20%, measured differentially
130
130
335
375
490
545
0.5
100
45
65
180
180
635
695
ps
ps
ps
ps
ps/°C
ps
ps
Ps
ps
ps
70
15
45
140
80
90
275
130
Output Rise Time, t
RL
Output Fall Time, t
FL
PROPAGATION DELAY, t
LVDS
, CLK-TO-LVDS OUT
1
OUT3 to OUT4
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS
OUT3 to OUT4 on Same Part, t
SKV2
All LVDS OUTs Across Multiple Parts, t
SKV_AB3
Same LVDS OUT Across Multiple Parts, t
SKV_AB3
CMOS
Output Rise Time, t
RC
Output Fall Time, t
FC
PROPAGATION DELAY, t
CMOS
, CLK-TO-CMOS OUT
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS
OUT3 to OUT4 on Same Part, t
SKC2
All CMOS OUT Across Multiple Parts, t
SKC_AB3
Same CMOS OUT Across Multiple Parts, t
SKC_AB3
LVPECL-TO-LVDS OUT
Output Skew, t
SKP_V
LVPECL-TO-CMOS OUT
Output Skew, t
SKP_C
LVDS-TO-CMOS OUT
Output Skew, t
SKV_C
200
210
350
350
ps
ps
Termination = 100 Ω differential
Output level 40h (41h) <2:1> = 01b
3.5 mA termination current
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT4
0.99
1.04
1.33
1.38
0.9
1.59
1.64
ns
ns
ps/°C
Delay off on OUT4
ps
ps
ps
ps
ps
ns
ns
ps/°C
Delay off on OUT4
B outputs are inverted; termination = open
20% to 80%; C
LOAD
= 3 pF
80% to 20%; C
LOAD
= 3 pF
Delay off on OUT4
−85
+270
450
325
681
646
865
992
1.71
1.76
1.02
1.07
1.39
1.44
1
+145
−140
+300
650
500
1.14
1.43
506
ps
ps
ns
ns
ps
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
Everything the same; different logic type
LVDS to CMOS on same part
0.74
0.88
158
0.92
1.14
353
Rev. A | Page 5 of 48
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