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AL10051N3DL 参数 Datasheet PDF下载

AL10051N3DL图片预览
型号: AL10051N3DL
PDF下载: 下载PDF文件 查看货源
内容描述: 薄膜片式电感器 [THIN FILM CHIP INDUCTOR]
分类和应用: 电感器
文件页数/大小: 66 页 / 368 K
品牌: ABC [ ABC Taiwan Electronics Corp ]
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AL103 Revision 1.0  
This mode of PHY management is very useful for unmanaged switches. The operating mode of the  
link can be changed by programming the mode pin of the PHY through a jumper.  
The AL103 also supports 100Base-TX transceivers without a MDIO interface or MII to MII  
interface. When MDIO is disabled, the AL103 will operate in the operation mode specified in the  
port configuration register (register 0D to 1C).  
3.13.4 Non Auto-negotiation Mode  
The AL103 can also turn off the auto-negotiation capability of the PHY. When auto-negotiation is  
turned off, the AL103 is in the slave mode and the transceiver will determine the link’s operating  
mode.  
3.13.5 Other PHY Options  
Some Legacy Fast Ethernet devices and other low cost devices have no auto-negotiation capability.  
In those cases when the transceiver will not be able to perform auto-negotiation, the switch  
transceiver will typically do a parallel detection and update the information in the transceiver’s  
register. Unfortunately, such register addresses are vendor specific. The AL103 provides a register  
(register 05) to specify the register address of the PHY for the AL103 to read. The AL103 will read  
from that register and configure the port operation accordingly.  
Register 05 also provides some additional flexibility’s for some of the PHYs in the market. In  
general, the system designer should set the ID of the PHY devices as 0 for port 0, 1 for port 1, and 7  
for port 7. Certain PHYs utilize PHY address 00000 as a broadcast address. Bit 1 of the register 05  
allows the AL103 to start with PHY address 01000. This provision allows the engineers to work  
around the PHY’s that have problems handling address 00000.  
Quad PHYs may have 2-port ordering in the chip pinout, both clockwise and counter clockwise.  
Register 05 bit 2, programs the AL103 port order to go in either direction. This provision enables  
engineers to easily implement designs with any PHY.  
There is also a slow MDIO clock (17 KHz) available for PHY that is not capable of handling a high  
speed MDIO clock.  
If for some reason, the transceiver is connected to a device and that device fails to auto-negotiate,  
the AL103 will default the data rate and duplex mode to the default setting in the port configuration  
register.  
3.14 EEPROM Interface  
The AL103 provides three functions with the EEPROM interface: system initialization, obtaining  
system status, and reconfiguring the system in real time. The AL103 uses the 24C02 serial  
EEPROM device (2048 bits organized as 256 bits x 8).  
3.14.1 System Initialization  
The EEPROM interface is provided so that the manufacturer can provide a pre-configured system  
to their customers which allows customers to change or reconfigure their system and retain their  
preferences. The EEPROM contains configuration and initialization information, which will be  
accessed at power up or reset.  
9/00  
Reference Only / Allayer Communications  
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